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From: Mika Westerberg <mika.westerberg@linux.intel.com>
Subject: Re: [PATCH v4] gpio: Add support for Intel SoC PMIC (Crystal Cove)
Date: Tue, 3 Jun 2014 13:57:10 +0300
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To: Linus Walleij <linus.walleij@linaro.org>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>, Alexandre Courbot <gnurou@gmail.com>, "Zhu, Lejun" <lejun.zhu@linux.intel.com>, Mathias Nyman <mathias.nyman@linux.intel.com>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, jacob.jun.pan@linux.intel.com, bin.yang@intel.com

On Tue, Jun 03, 2014 at 10:10:13AM +0200, Linus Walleij wrote:
> On Fri, May 30, 2014 at 10:25 AM, Mika Westerberg
> <mika.westerberg@linux.intel.com> wrote:
> 
> > I'm thinking that could we solve this so that we call
> > acpi_gpiochip_request_interrupts() at the end of gpiochip_irqchip_add()
> > and convert both pinctrl-baytrail and gpio-lynxpoint to use
> > gpiochip_irqchip_add()?
> 
> Yes that seems like a great way to solve it actually.
> 
> Is someone able to do this refactoring?

I have both Haswell and Baytrail hardware here so I can take a look if I
have time.

> I don't know if you have a case of an ACPI-based GPIO controller
> that is *not* supplying interrupts? Because in that case this
> would even be required for the thing to work, right?

Both Haswell and Baytrail support interrupts but only the later provides
ACPI events as far as I can tell.