From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45034) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws5BE-0005Ys-SB for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:00:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ws5B8-0002qJ-Sb for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:00:12 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:54485) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ws5B8-0002nf-Hb for qemu-devel@nongnu.org; Wed, 04 Jun 2014 03:00:06 -0400 Received: by mail-pd0-f177.google.com with SMTP id g10so5683903pdj.22 for ; Wed, 04 Jun 2014 00:00:05 -0700 (PDT) Date: Wed, 4 Jun 2014 08:52:25 +0200 From: "Edgar E. Iglesias" Message-ID: <20140604065225.GE3378@toto> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-8-git-send-email-edgar.iglesias@gmail.com> <87k38ys2xg.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87k38ys2xg.fsf@linaro.org> Subject: Re: [Qemu-devel] [PATCH v1 07/16] target-arm: Add HCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, rob.herring@linaro.org, aggelerf@ethz.ch, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, john.williams@xilinx.com, greg.bellows@linaro.org, pbonzini@redhat.com, christoffer.dall@linaro.org, rth@twiddle.net On Tue, Jun 03, 2014 at 11:27:55AM +0100, Alex Bennée wrote: > > Edgar E. Iglesias writes: > > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target-arm/cpu.h | 35 +++++++++++++++++++++++++++++++++++ > > target-arm/helper.c | 27 +++++++++++++++++++++++++++ > > 2 files changed, 62 insertions(+) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index ef6a95d..b446478 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -184,6 +184,7 @@ typedef struct CPUARMState { > > MPU write buffer control. */ > > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > > + uint64_t hcr_el2; /* Hypervisor configuration register */ > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > @@ -526,6 +527,40 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) > > } > > } > > > > +#define HCR_VM (1ULL << 0) > > +#define HCR_SWIO (1ULL << 1) > > +#define HCR_PTW (1ULL << 2) > > +#define HCR_FMO (1ULL << 3) > > +#define HCR_IMO (1ULL << 4) > > +#define HCR_AMO (1ULL << 5) > > +#define HCR_VF (1ULL << 6) > > +#define HCR_VI (1ULL << 7) > > +#define HCR_VSE (1ULL << 8) > > +#define HCR_FB (1ULL << 9) > > +#define HCR_DC (1ULL << 12) > > +#define HCR_TWI (1ULL << 13) > > +#define HCR_TWE (1ULL << 14) > > +#define HCR_TID0 (1ULL << 15) > > +#define HCR_TID1 (1ULL << 16) > > +#define HCR_TID2 (1ULL << 17) > > +#define HCR_TID3 (1ULL << 18) > > +#define HCR_TSC (1ULL << 19) > > +#define HCR_TIDCP (1ULL << 20) > > +#define HCR_TACR (1ULL << 21) > > +#define HCR_TSW (1ULL << 22) > > +#define HCR_TPC (1ULL << 23) > > +#define HCR_TPU (1ULL << 24) > > +#define HCR_TTLB (1ULL << 25) > > +#define HCR_TVM (1ULL << 26) > > +#define HCR_TGE (1ULL << 27) > > +#define HCR_TDZ (1ULL << 28) > > +#define HCR_HCD (1ULL << 29) > > +#define HCR_TRVM (1ULL << 30) > > +#define HCR_RW (1ULL << 31) > > +#define HCR_CD (1ULL << 32) > > +#define HCR_ID (1ULL << 33) > > +#define HCR_RES0_MASK ((1ULL << 34) - 1) > > Hmm isn't that actually HCR_MASK? I would expect the mask for the RES0 > bits to be ~((1ULL << 34) - 1) but it's not actually used for that hence > the name confusion. I can change the name for v2, thanks. > > > + > > /* Return the current FPSCR value. */ > > uint32_t vfp_get_fpscr(CPUARMState *env); > > void vfp_set_fpscr(CPUARMState *env, uint32_t val); > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index de5ee40..cf877ae 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2107,10 +2107,37 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { > > .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, > > .access = PL2_RW, > > .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > > + { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, > > + .type = ARM_CP_NO_MIGRATE, > > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > > REGINFO_SENTINEL > > }; > > > > +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > > +{ > > + ARMCPU *cpu = arm_env_get_cpu(env); > > + uint64_t res0_mask = HCR_RES0_MASK; > > + > > + if (!arm_feature(env, ARM_FEATURE_EL3)) { > > + res0_mask &= ~HCR_HCD; > > + } > > + > > + /* Clear RES0 bits. */ > > + value &= res0_mask; > > + > > + if ((raw_read(env, ri) ^ value) & HCR_VM) { > > + /* Flush the TLB when turning VM on/off. */ > > + tlb_flush(CPU(cpu), 1); > > + } > > + raw_write(env, ri, value); > > +} > > + > > static const ARMCPRegInfo v8_el2_cp_reginfo[] = { > > + { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > > + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), > > + .writefn = hcr_write }, > > { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, > > .type = ARM_CP_NO_MIGRATE, > > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, > > -- > Alex Bennée