From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH 1/3] drm/tegra: Align FB pitch Date: Thu, 5 Jun 2014 11:40:49 +0200 Message-ID: <20140605094048.GA23296@ulmo> References: <1400896714-7092-1-git-send-email-marcheu@chromium.org> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2001208744==" Return-path: Received: from mail-we0-f171.google.com (mail-we0-f171.google.com [74.125.82.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 04A076E934 for ; Thu, 5 Jun 2014 02:43:36 -0700 (PDT) Received: by mail-we0-f171.google.com with SMTP id w62so782377wes.16 for ; Thu, 05 Jun 2014 02:43:36 -0700 (PDT) In-Reply-To: <1400896714-7092-1-git-send-email-marcheu@chromium.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: =?utf-8?B?U3TDqXBoYW5l?= Marchesin Cc: treding@nvidia.com, dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============2001208744== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9amGYk9869ThD9tj" Content-Disposition: inline --9amGYk9869ThD9tj Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, May 23, 2014 at 06:58:32PM -0700, St=C3=A9phane Marchesin wrote: > The display controller doesn't handle non-256 byte aligned buffer > pitches. If you give it an unaligned buffer, it will stop after the > first line and will report underflows in the debug registers > (DC_WINBUF_UFLOW_STATUS and friends). So let's make sure that all our > framebuffer pitches are 256-byte aligned. >=20 > Signed-off-by: St=C3=A9phane Marchesin > --- > drivers/gpu/drm/tegra/drm.h | 2 ++ > drivers/gpu/drm/tegra/fb.c | 3 ++- > drivers/gpu/drm/tegra/gem.c | 2 ++ > 3 files changed, 6 insertions(+), 1 deletion(-) Can you point me to where this requirement is documented? I've gone through the TRM and all I can find is that the line stride needs to be 64 byte aligned. Also I seem to remember that resolutions such as 1366x768 used to work for HDMI at least on earlier Tegra generations. Perhaps this is a requirement that's new on Tegra124? Thierry --9amGYk9869ThD9tj Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAEBAgAGBQJTkDsgAAoJEN0jrNd/PrOhPZoQAMDV1wcIxKCHH9gwpAVhTnDX M82a2Op8ltjf0mgUWWtUsQYzhkP8VJiphGgc6icvbkxcZN9OT0e4v4yZE/n4oIWs QW42AXK/KtOL4VkPpcTqJgCK0NXfyGz10dvcqcnD3g+JMelgdOJu9nIAnoxV+OW8 UDgr0fftBdxHRDVB2srSBK63iJWLLR/a7TlQZYn+RBaieF5hp2swt4b/+NDbpAgO a2eKJtZ8rJn8UrMVurGol5Aepxy3RpWpWPEgToqqFkjfSWioPj1lljtGAh+9zhLc vX457+CbKe429fk4CHI0VKXW+ueebH/P0eVbfF4j//sPKZfRAl9rNeyB6A5tf/C7 qkVvTtioXdeAguygEjo0jDiXD8Bev1653PS+g2tIqx4rGdWYZnaYFUFDRBXywJs/ fdUxT0j7WPdw3QBNg5l9lg+5DAMIIw1ycHXg6Of332QClw0Dx9YixmxKIeERL5WY PjviPX+dd/vNpjK9MrgEQn80uDuh45/xsrrpT1Oi5KiVOJ2mMnzQFtgz4uM2lhEa L65UPc8TTkXfTE8PCiw4m2FWL8ln/dil4Jii+y9bWObx5B2nHgnzW0RP4gCgvQ+f KrM/57Go6UkDBi/vbIrF4j7DOLzVxLM4WgNuhwduwseU/HFnEHtCTq/6t2puGuas iLes1DTMoe8fyrr+dPpm =24n4 -----END PGP SIGNATURE----- --9amGYk9869ThD9tj-- --===============2001208744== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel --===============2001208744==--