From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39684) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wtml8-0004KQ-1k for qemu-devel@nongnu.org; Sun, 08 Jun 2014 19:44:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wtml2-0006El-2h for qemu-devel@nongnu.org; Sun, 08 Jun 2014 19:44:17 -0400 Received: from mail-pa0-x22a.google.com ([2607:f8b0:400e:c03::22a]:63942) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wtml1-0006EW-P2 for qemu-devel@nongnu.org; Sun, 08 Jun 2014 19:44:11 -0400 Received: by mail-pa0-f42.google.com with SMTP id lj1so140341pab.1 for ; Sun, 08 Jun 2014 16:44:10 -0700 (PDT) Date: Mon, 9 Jun 2014 09:43:40 +1000 From: "Edgar E. Iglesias" Message-ID: <20140608234340.GV18802@zapo.iiNet> References: <1401434911-26992-1-git-send-email-edgar.iglesias@gmail.com> <1401434911-26992-12-git-send-email-edgar.iglesias@gmail.com> <3A45136B-A2A8-4363-90A6-436047C0C347@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3A45136B-A2A8-4363-90A6-436047C0C347@ethz.ch> Subject: Re: [Qemu-devel] [PATCH v1 11/16] target-arm: Don't take interrupts targeting lower ELs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aggeler Fabian Cc: "peter.maydell@linaro.org" , "peter.crosthwaite@xilinx.com" , "rob.herring@linaro.org" , "qemu-devel@nongnu.org" , "agraf@suse.de" , "blauwirbel@gmail.com" , "john.williams@xilinx.com" , "greg.bellows@linaro.org" , "pbonzini@redhat.com" , "alex.bennee@linaro.org" , "christoffer.dall@linaro.org" , "rth@twiddle.net" On Sun, Jun 08, 2014 at 03:51:24PM +0000, Aggeler Fabian wrote: > > On 30 May 2014, at 09:28, Edgar E. Iglesias wrote: > > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target-arm/cpu.h | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 9eddcc1..66c58bd 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -1133,6 +1133,13 @@ bool write_cpustate_to_list(ARMCPU *cpu); > > static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) > > { > > CPUARMState *env = cs->env_ptr; > > + unsigned int cur_el = arm_current_pl(env); > > + unsigned int target_el = arm_excp_target_el(cs, excp_idx); > > + > > + /* Don't take exceptions if they target a lower EL. */ > > + if (cur_el > target_el) { > > + return false; > > + } > > Hi Edgar Hi Fabian, > > When making arm_excp_unmasked() reflect tables D1-13, D1-14, D1-15 > and G1-18, G1-19 in ARM ARMv8 this should not be necessary if I am > not mistaken. Cases in which target_el is lower than cur_el are marked with > a P (pending) in the table. Or am I missing something interpreting the > tables? This function is called to check if we can take a pending interrupt or exception with current CPU state. It does not clear pending exceptions. In this case, if the target_el is lower than the current EL we return false and leave the exception pending (to be taken later). > > I extended your arm_excp_unmasked() and arm_excp_target_el() to reflect > the behaviour shown in the tables in ARM ARMv8 and ARM ARMv7. I will > send them with the TZ patches. Great, thanks. Cheers, Edgar > > Best, > Fabian > > > > > switch (excp_idx) { > > case EXCP_FIQ: > > -- > > 1.8.3.2 > > >