diff for duplicates of <20140612181919.038012f5@xhacker> diff --git a/a/1.txt b/N1/1.txt index 763f305..c28fdc6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,12 +1,12 @@ Hi Russell, On Thu, 12 Jun 2014 03:15:03 -0700 -Jisheng Zhang <jszhang@marvell.com> wrote: +Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> wrote: > Hi Russell, > > On Thu, 12 Jun 2014 02:44:23 -0700 -> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote: +> Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote: > > > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote: > > > For all BG2Q SoCs, 2 cycles is the best/correct value @@ -23,3 +23,7 @@ The BG2Q L2 cache controller is PL310, so no "dirty-latency" Thanks, Jisheng +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 867b4b3..ea235da 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,21 +1,32 @@ "ref\01402565920-5636-1-git-send-email-jszhang@marvell.com\0" "ref\020140612094423.GC23430@n2100.arm.linux.org.uk\0" "ref\020140612181503.06562a38@xhacker\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0" + "From\0Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\0" + "Subject\0Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0" "Date\0Thu, 12 Jun 2014 18:19:19 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>\0" + "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>" + pawel.moll-5wv7dgnIgG8@public.gmane.org <pawel.moll-5wv7dgnIgG8@public.gmane.org> + mark.rutland-5wv7dgnIgG8@public.gmane.org <mark.rutland-5wv7dgnIgG8@public.gmane.org> + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>\0" "\00:1\0" "b\0" "Hi Russell,\n" "\n" "On Thu, 12 Jun 2014 03:15:03 -0700\n" - "Jisheng Zhang <jszhang@marvell.com> wrote:\n" + "Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> wrote:\n" "\n" "> Hi Russell,\n" "> \n" "> On Thu, 12 Jun 2014 02:44:23 -0700\n" - "> Russell King - ARM Linux <linux@arm.linux.org.uk> wrote:\n" + "> Russell King - ARM Linux <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:\n" "> \n" "> > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:\n" "> > > For all BG2Q SoCs, 2 cycles is the best/correct value\n" @@ -31,6 +42,10 @@ "The BG2Q L2 cache controller is PL310, so no \"dirty-latency\"\n" "\n" "Thanks,\n" - Jisheng + "Jisheng\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -2a75e6630503beff501dfe33c374186da4264b4af291c69db343d81ad832a1af +151dbfc166f55fe3b16cc5b70e8aa2cb98f8083985c1b70dcfcdefabdcac6e4c
diff --git a/a/content_digest b/N2/content_digest index 867b4b3..bb83e52 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,21 @@ "ref\01402565920-5636-1-git-send-email-jszhang@marvell.com\0" "ref\020140612094423.GC23430@n2100.arm.linux.org.uk\0" "ref\020140612181503.06562a38@xhacker\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0" + "From\0Jisheng Zhang <jszhang@marvell.com>\0" + "Subject\0Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles\0" "Date\0Thu, 12 Jun 2014 18:19:19 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Russell King - ARM Linux <linux@arm.linux.org.uk>\0" + "Cc\0robh+dt@kernel.org <robh+dt@kernel.org>" + pawel.moll@arm.com <pawel.moll@arm.com> + mark.rutland@arm.com <mark.rutland@arm.com> + ijc+devicetree@hellion.org.uk <ijc+devicetree@hellion.org.uk> + galak@codeaurora.org <galak@codeaurora.org> + sebastian.hesselbarth@gmail.com <sebastian.hesselbarth@gmail.com> + alexandre.belloni@free-electrons.com <alexandre.belloni@free-electrons.com> + antoine.tenart@free-electrons.com <antoine.tenart@free-electrons.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "Hi Russell,\n" @@ -33,4 +44,4 @@ "Thanks,\n" Jisheng -2a75e6630503beff501dfe33c374186da4264b4af291c69db343d81ad832a1af +cc02bd5a1d994e0318afc1d02318c2670333aacd817f76dba6ba143de71b664a
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