From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 2/4] drm/i915/vlv: Ack interrupts before handling them (VLV) Date: Mon, 16 Jun 2014 16:05:08 +0300 Message-ID: <20140616130508.GI27580@intel.com> References: <1402918229-7246-1-git-send-email-oscar.mateo@intel.com> <1402918229-7246-2-git-send-email-oscar.mateo@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A6C26E538 for ; Mon, 16 Jun 2014 06:05:14 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1402918229-7246-2-git-send-email-oscar.mateo@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: oscar.mateo@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Jun 16, 2014 at 12:30:27PM +0100, oscar.mateo@intel.com wrote: > From: Oscar Mateo > = > Otherwise, we might receive a new interrupt before we have time to > ack the first one, eventually missing it. > = > Notice that, before clearing a port-sourced interrupt in the IIR, the > corresponding interrupt source status in the PORT_HOTPLUG_STAT must be > cleared. I believe PIPESTAT (and actually all multi-level interrupts) should be handled the same way. The way I would write interrupt handlers is something like this: { iir =3D read(IIR); if (iir & X) { iir_x =3D read(IIR_X); write(IIR_X, iir_x); } if (iir & Y) { iir_y =3D read(IIR_Y); write(IIR_Y, iir_y); } ... write(IIR, iir); = process_x(iir_x); process_y(iir_y); ... } And then we hope the hardware is sane enough to keep the IIR bit high as long as the relevant sub-IIR bits are high, and also that the CPU interrupt would be re-raised if any IIR bits are high when exiting the interrupt handler. But I have the impression our hardware isn't quite that sane. > = > Spotted by Bob Beckett . > = > Signed-off-by: Oscar Mateo > --- > drivers/gpu/drm/i915/i915_irq.c | 61 +++++++++++++++++++++++------------= ------ > 1 file changed, 35 insertions(+), 26 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index 4439e2d..9d381cc 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1813,26 +1813,28 @@ static void i9xx_hpd_irq_handler(struct drm_devic= e *dev) > struct drm_i915_private *dev_priv =3D dev->dev_private; > u32 hotplug_status =3D I915_READ(PORT_HOTPLUG_STAT); > = > - if (IS_G4X(dev)) { > - u32 hotplug_trigger =3D hotplug_status & HOTPLUG_INT_STATUS_G4X; > + if (hotplug_status) { > + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + /* > + * Make sure hotplug status is cleared before we clear IIR, or else we > + * may miss hotplug events. > + */ > + POSTING_READ(PORT_HOTPLUG_STAT); > = > - intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); > - } else { > - u32 hotplug_trigger =3D hotplug_status & HOTPLUG_INT_STATUS_I915; > + if (IS_G4X(dev)) { > + u32 hotplug_trigger =3D hotplug_status & HOTPLUG_INT_STATUS_G4X; > = > - intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); > - } > + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x); > + } else { > + u32 hotplug_trigger =3D hotplug_status & HOTPLUG_INT_STATUS_I915; > = > - if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && > - hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) > - dp_aux_irq_handler(dev); > + intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); > + } > = > - I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > - /* > - * Make sure hotplug status is cleared before we clear IIR, or else we > - * may miss hotplug events. > - */ > - POSTING_READ(PORT_HOTPLUG_STAT); > + if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && > + hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) > + dp_aux_irq_handler(dev); > + } > } > = > static irqreturn_t valleyview_irq_handler(int irq, void *arg) > @@ -1843,29 +1845,36 @@ static irqreturn_t valleyview_irq_handler(int irq= , void *arg) > irqreturn_t ret =3D IRQ_NONE; > = > while (true) { > - iir =3D I915_READ(VLV_IIR); > gt_iir =3D I915_READ(GTIIR); > pm_iir =3D I915_READ(GEN6_PMIIR); > + iir =3D I915_READ(VLV_IIR); > = > if (gt_iir =3D=3D 0 && pm_iir =3D=3D 0 && iir =3D=3D 0) > goto out; > = > - ret =3D IRQ_HANDLED; > + if (gt_iir) > + I915_WRITE(GTIIR, gt_iir); > = > - snb_gt_irq_handler(dev, dev_priv, gt_iir); > + if (pm_iir) > + I915_WRITE(GEN6_PMIIR, pm_iir); > = > - valleyview_pipestat_irq_handler(dev, iir); > + if (iir) { > + /* Consume port. Then clear IIR or we'll miss events */ > + if (iir & I915_DISPLAY_PORT_INTERRUPT) > + i9xx_hpd_irq_handler(dev); > + I915_WRITE(VLV_IIR, iir); > + } > = > - /* Consume port. Then clear IIR or we'll miss events */ > - if (iir & I915_DISPLAY_PORT_INTERRUPT) > - i9xx_hpd_irq_handler(dev); > + ret =3D IRQ_HANDLED; > + > + if (gt_iir) > + snb_gt_irq_handler(dev, dev_priv, gt_iir); > = > if (pm_iir) > gen6_rps_irq_handler(dev_priv, pm_iir); > = > - I915_WRITE(GTIIR, gt_iir); > - I915_WRITE(GEN6_PMIIR, pm_iir); > - I915_WRITE(VLV_IIR, iir); > + if (iir) > + valleyview_pipestat_irq_handler(dev, iir); > } > = > out: > -- = > 1.9.0 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC