From: Andi Kleen <ak@linux.intel.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
"mingo@elte.hu" <mingo@elte.hu>, Joe Mario <jmario@redhat.com>,
Don Zickus <dzickus@redhat.com>, Jiri Olsa <jolsa@redhat.com>,
Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: Re: [PATCH 1/2] perf/x86: update Haswell PEBS event constraints
Date: Mon, 23 Jun 2014 08:47:51 -0700 [thread overview]
Message-ID: <20140623154751.GE8178@tassilo.jf.intel.com> (raw)
In-Reply-To: <20140623113759.GD13930@laptop.programming.kicks-ass.net>
> Filters? You mean the inv,cmask etc? Well, we have the Intel provided
> 'cycle' events that use them, so exposing them makes sense and allows
> such experimentation when we need another such alias.
The SDM explicitely discourages it.
The 'cycle' event is now handled explicitely, but for others it is still
not ok.
-Andi
next prev parent reply other threads:[~2014-06-23 15:48 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 15:58 [PATCH 0/2] perf/x86: improve Intel load latency and precise store event constraints Stephane Eranian
2014-06-19 15:58 ` [PATCH 1/2] perf/x86: update Haswell PEBS " Stephane Eranian
2014-06-19 18:00 ` Andi Kleen
2014-06-19 19:53 ` Stephane Eranian
2014-06-19 20:18 ` Andi Kleen
2014-06-19 20:31 ` Stephane Eranian
2014-06-19 20:40 ` Andi Kleen
2014-06-19 20:45 ` Stephane Eranian
2014-06-20 13:44 ` Stephane Eranian
2014-06-23 7:35 ` Peter Zijlstra
2014-06-23 14:16 ` Andi Kleen
2014-06-23 7:14 ` Peter Zijlstra
2014-06-23 8:06 ` Stephane Eranian
2014-06-23 11:37 ` Peter Zijlstra
2014-06-23 11:51 ` Stephane Eranian
2014-06-23 15:47 ` Andi Kleen [this message]
2014-06-23 7:12 ` Peter Zijlstra
2014-06-19 15:58 ` [PATCH 2/2] perf/x86: fix constraints for load latency and precise events Stephane Eranian
2014-06-19 20:56 ` Andi Kleen
2014-06-23 8:42 ` Peter Zijlstra
2014-06-23 9:00 ` Stephane Eranian
2014-06-23 11:39 ` Peter Zijlstra
2014-06-23 14:22 ` Andi Kleen
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