Re: [Qemu-devel] [PATCH v4 02/33] target-arm: move Aarch32 SCR into security reglist

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Mon, Jun 30, 2014 at 06:09:02PM -0500, greg.bellows@linaro.org wrote:
> From: Fabian Aggeler <aggelerf@ethz.ch>
> 
> Define a new ARM CP register info list for the ARMv7 Security Extension
> feature. Register that list only for ARM cores with Security Extension/EL3
> support. Moving Aarch32 SCR into Security Extension register group.
> 
> Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>



> 
> ------------------
> v3 -> v4
> - Renamed security_cp_reginfo to v7_el3_cp_reginfo
> - Conditionalized define on whether v7 or v8 were enabled
> 
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> ---
>  target-arm/helper.c | 17 +++++++++++++----
>  1 file changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 7c4b801..1ea30fe 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -792,9 +792,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>        .access = PL1_RW, .writefn = vbar_write,
>        .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
>        .resetvalue = 0 },
> -    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> -      .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> -      .resetvalue = 0, },
>      { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
>        .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
> @@ -2227,6 +2224,13 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
>      REGINFO_SENTINEL
>  };
>  
> +static const ARMCPRegInfo v7_el3_cp_reginfo[] = {
> +    { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> +      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
> +      .resetvalue = 0, },
> +    REGINFO_SENTINEL
> +};
> +
>  static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                          uint64_t value)
>  {
> @@ -2489,7 +2493,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>          }
>      }
>      if (arm_feature(env, ARM_FEATURE_EL3)) {
> -        define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
> +        if (arm_feature(env, ARM_FEATURE_V8)) {
> +            define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
> +        }
> +        if (arm_feature(env, ARM_FEATURE_V7)) {
> +            define_arm_cp_regs(cpu, v7_el3_cp_reginfo);
> +        }
>      }
>      if (arm_feature(env, ARM_FEATURE_MPU)) {
>          /* These are the MPU registers prior to PMSAv6. Any new
> -- 
> 1.8.3.2
>