From: Andi Kleen <andi@firstfloor.org>
To: kan.liang@intel.com
Cc: peterz@infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, andi@firstfloor.org
Subject: Re: [PATCH V2 2/3] perf protect LBR when Intel PT is enabled.
Date: Thu, 3 Jul 2014 04:44:20 +0200 [thread overview]
Message-ID: <20140703024420.GO5714@two.firstfloor.org> (raw)
In-Reply-To: <1404324855-15166-2-git-send-email-kan.liang@intel.com>
On Wed, Jul 02, 2014 at 11:14:14AM -0700, kan.liang@intel.com wrote:
> From: Kan Liang <kan.liang@intel.com>
>
> If RTIT_CTL.TraceEn=1, any attempt to read or write the LBR or LER MSRs, including LBR_TOS, will result in a #GP.
> Since Intel PT can be enabled/disabled at runtime, LBR MSRs have to be protected by _safe() at runtime.
>
> Signed-off-by: Kan Liang <kan.liang@intel.com>
Patch looks good to me.
-Andi
next prev parent reply other threads:[~2014-07-03 2:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-02 18:14 [PATCH V2 1/3] perf ignore LBR and offcore_rsp kan.liang
2014-07-02 18:14 ` [PATCH V2 2/3] perf protect LBR when Intel PT is enabled kan.liang
2014-07-03 2:44 ` Andi Kleen [this message]
2014-07-03 7:33 ` Peter Zijlstra
2014-07-03 15:52 ` Andi Kleen
2014-07-03 17:07 ` Peter Zijlstra
2014-07-07 13:57 ` Liang, Kan
2014-07-07 15:46 ` Peter Zijlstra
2014-07-07 15:47 ` Peter Zijlstra
2014-07-02 18:14 ` [PATCH V2 3/3] kvm: ignore LBR and offcore rsp kan.liang
2014-07-03 2:16 ` [PATCH V2 1/3] perf ignore LBR and offcore_rsp Andi Kleen
2014-07-03 4:26 ` Liang, Kan
2014-07-03 2:29 ` Jidong Xiao
2014-07-03 4:26 ` Liang, Kan
2014-07-03 4:26 ` Liang, Kan
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