From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Correctly read backlight PWM for pipe B on vlv/chv Date: Tue, 29 Jul 2014 16:13:04 +0300 Message-ID: <20140729131304.GX27580@intel.com> References: <1406637880-6918-1-git-send-email-rafael.barbalho@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B5F26E19D for ; Tue, 29 Jul 2014 06:13:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1406637880-6918-1-git-send-email-rafael.barbalho@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: rafael.barbalho@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jul 29, 2014 at 01:44:40PM +0100, rafael.barbalho@intel.com wrote: > From: Rafael Barbalho > = > Make the vlv/chv backlight setup more generic by actually looking at which > pipe the panel is attached to and read the backlight PWM registers that w= ere > setup by the bios from that pipe. > = > Cc: Ville Syrj=E4l=E4 > Signed-off-by: Rafael Barbalho > --- > drivers/gpu/drm/i915/intel_panel.c | 24 ++++++++++-------------- > 1 file changed, 10 insertions(+), 14 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/in= tel_panel.c > index 59b028f..be75d76 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -1200,32 +1200,28 @@ static int vlv_setup_backlight(struct intel_conne= ctor *connector) > struct drm_device *dev =3D connector->base.dev; > struct drm_i915_private *dev_priv =3D dev->dev_private; > struct intel_panel *panel =3D &connector->panel; > - enum pipe pipe; > + enum pipe pipe =3D intel_get_pipe_from_connector(connector); This won't work unless the connector is already enabled. The power sequencer has a similar problem where we have to somehow deduce the correct pipe. vlv_power_sequencer_pipe() tries to guess the correct pipe there. We could start with intel_get_pipe_from_connector() and if that fails we'd do something like vlv_power_sequencer_pipe(). Hmm, except the backlight registers don't have the port information, so I guess we'd need to pick the pipe simply based on the DP port control register. > u32 ctl, ctl2, val; > = > - for_each_pipe(pipe) { > - u32 cur_val =3D I915_READ(VLV_BLC_PWM_CTL(pipe)); > + ctl2 =3D I915_READ(VLV_BLC_PWM_CTL2(pipe)); > + panel->backlight.active_low_pwm =3D ctl2 & BLM_POLARITY_I965; > = > - /* Skip if the modulation freq is already set */ > - if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) > - continue; > + ctl =3D I915_READ(VLV_BLC_PWM_CTL(pipe)); > = > - cur_val &=3D BACKLIGHT_DUTY_CYCLE_MASK; > - I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | > - cur_val); > + /* Skip if the modulation freq is already set */ > + if ((ctl & ~BACKLIGHT_DUTY_CYCLE_MASK) =3D=3D 0) { > + ctl &=3D BACKLIGHT_DUTY_CYCLE_MASK; > + ctl |=3D (0xf42 << 16); > + I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); > } > = > - ctl2 =3D I915_READ(VLV_BLC_PWM_CTL2(PIPE_A)); > - panel->backlight.active_low_pwm =3D ctl2 & BLM_POLARITY_I965; > - > - ctl =3D I915_READ(VLV_BLC_PWM_CTL(PIPE_A)); > panel->backlight.max =3D ctl >> 16; > if (!panel->backlight.max) > return -ENODEV; > = > panel->backlight.min =3D get_backlight_min_vbt(connector); > = > - val =3D _vlv_get_backlight(dev, PIPE_A); > + val =3D _vlv_get_backlight(dev, pipe); > panel->backlight.level =3D intel_panel_compute_brightness(connector, va= l); > = > panel->backlight.enabled =3D (ctl2 & BLM_PWM_ENABLE) && > -- = > 2.0.3 -- = Ville Syrj=E4l=E4 Intel OTC