From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines
Date: Fri, 1 Aug 2014 14:26:46 +0300 [thread overview]
Message-ID: <20140801112646.GV4193@intel.com> (raw)
In-Reply-To: <CA+gsUGQK3Aqf1QK8acrzTT+gYxdsUvbjyRqsvp5m4j+iDWS4ag@mail.gmail.com>
On Thu, Jul 31, 2014 at 05:16:21PM -0300, Paulo Zanoni wrote:
> 2014-06-27 20:04 GMT-03:00 <ville.syrjala@linux.intel.com>:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Add defines for all the watermark registers on modernish gmch platforms.
> >
> > VLV has increased the number of bits available for certain watermaks so
> > expand the masks appropriately. Also vlv and chv have added some extra
> > FW registers.
> >
> > Not sure what happened on chv because a new register called FW9 is now
> > at the offset where FW7 was on vlv, while FW7 and FW8 (another new
> > register) have been moved off somewhere else. Oh well, well just need
> > two defines for FW7 then.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 138 +++++++++++++++++++++++++++++++++++-----
> > drivers/gpu/drm/i915/intel_pm.c | 11 ++--
> > 2 files changed, 130 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7ab5a03..9fab647 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3884,28 +3884,136 @@ enum punit_power_well {
> > #define DSPARB_BEND_SHIFT 9 /* on 855 */
> > #define DSPARB_AEND_SHIFT 0
> >
> > +/* pnv/gen4/g4x/vlv/chv */
> > #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
> > -#define DSPFW_SR_SHIFT 23
> > -#define DSPFW_SR_MASK (0x1ff<<23)
> > -#define DSPFW_CURSORB_SHIFT 16
> > -#define DSPFW_CURSORB_MASK (0x3f<<16)
> > -#define DSPFW_PLANEB_SHIFT 8
> > -#define DSPFW_PLANEB_MASK (0x7f<<8)
> > -#define DSPFW_PLANEA_MASK (0x7f)
> > +#define DSPFW_SR_SHIFT 23
> > +#define DSPFW_SR_MASK (0x1ff<<23)
> > +#define DSPFW_CURSORB_SHIFT 16
> > +#define DSPFW_CURSORB_MASK (0x3f<<16)
> > +#define DSPFW_PLANEB_SHIFT 8
> > +#define DSPFW_PLANEB_MASK (0x7f<<8)
> > +#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
> > +#define DSPFW_PLANEA_SHIFT 0
> > +#define DSPFW_PLANEA_MASK (0x7f<<0)
> > +#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
> > #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
> > -#define DSPFW_CURSORA_MASK 0x00003f00
> > -#define DSPFW_CURSORA_SHIFT 8
> > -#define DSPFW_PLANEC_MASK (0x7f)
> > +#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
> > +#define DSPFW_FBC_SR_SHIFT 28
> > +#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
> > +#define DSPFW_FBC_HPLL_SR_SHIFT 24
> > +#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
> > +#define DSPFW_SPRITEB_SHIFT (16)
> > +#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
> > +#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
> > +#define DSPFW_CURSORA_SHIFT 8
> > +#define DSPFW_CURSORA_MASK (0x3f<<8)
> > +#define DSPFW_PLANEC_SHIFT_OLD 0
> > +#define DSPFW_PLANEC_MASK_OLD (0x7f<<0) /* pre-gen4 sprite C */
> > +#define DSPFW_SPRITEA_SHIFT 0
> > +#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
> > +#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
> > #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
> > -#define DSPFW_HPLL_SR_EN (1<<31)
> > -#define DSPFW_CURSOR_SR_SHIFT 24
> > +#define DSPFW_HPLL_SR_EN (1<<31)
> > #define PINEVIEW_SELF_REFRESH_EN (1<<30)
> > +#define DSPFW_CURSOR_SR_SHIFT 24
> > #define DSPFW_CURSOR_SR_MASK (0x3f<<24)
> > #define DSPFW_HPLL_CURSOR_SHIFT 16
> > #define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
> > -#define DSPFW_HPLL_SR_MASK (0x1ff)
> > -#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
> > -#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
> > +#define DSPFW_HPLL_SR_SHIFT 0
> > +#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
> > +
> > +/* vlv/chv */
> > +#define DSPFW4 (VLV_DISPLAY_BASE + 0x70070)
> > +#define DSPFW_SPRITEB_WM1_SHIFT 16
> > +#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
> > +#define DSPFW_CURSORA_WM1_SHIFT 8
> > +#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
> > +#define DSPFW_SPRITEA_WM1_SHIFT 0
> > +#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
> > +#define DSPFW5 (VLV_DISPLAY_BASE + 0x70074)
> > +#define DSPFW_PLANEB_WM1_SHIFT 24
> > +#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
> > +#define DSPFW_PLANEA_WM1_SHIFT 16
> > +#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
> > +#define DSPFW_CURSORB_WM1_SHIFT 8
> > +#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
> > +#define DSPFW_CURSOR_SR_WM1_SHIFT 0
> > +#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
> > +#define DSPFW6 (VLV_DISPLAY_BASE + 0x70078)
> > +#define DSPFW_SR_WM1_SHIFT 0
> > +#define DSPFW_SR_WM1_MASK (0x1ff<<0)
> > +#define DSPFW7 (VLV_DISPLAY_BASE + 0x7007c)
> > +#define DSPFW7_CHV (VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
> > +#define DSPFW_SPRITED_WM1_SHIFT 24
> > +#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
> > +#define DSPFW_SPRITED_SHIFT 16
> > +#define DSPFW_SPRITED_MASK (0xff<<16)
> > +#define DSPFW_SPRITEC_WM1_SHIFT 8
> > +#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
> > +#define DSPFW_SPRITEC_SHIFT 0
> > +#define DSPFW_SPRITEC_MASK (0xff<<0)
> > +#define DSPFW8_CHV (VLV_DISPLAY_BASE + 0x700b8)
> > +#define DSPFW_SPRITEF_WM1_SHIFT 24
> > +#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
> > +#define DSPFW_SPRITEF_SHIFT 16
> > +#define DSPFW_SPRITEF_MASK (0xff<<16)
> > +#define DSPFW_SPRITEE_WM1_SHIFT 8
> > +#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
> > +#define DSPFW_SPRITEE_SHIFT 0
> > +#define DSPFW_SPRITEE_MASK (0xff<<0)
> > +#define DSPFW9_CHV (VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
> > +#define DSPFW_PLANEC_WM1_SHIFT 24
> > +#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
> > +#define DSPFW_PLANEC_SHIFT 16
> > +#define DSPFW_PLANEC_MASK (0xff<<16)
> > +#define DSPFW_CURSORC_WM1_SHIFT 8
> > +#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
> > +#define DSPFW_CURSORC_SHIFT 0
> > +#define DSPFW_CURSORC_MASK (0x3f<<0)
> > +
> > +/* vlv/chv high order bits */
> > +#define DSPHOWM (VLV_DISPLAY_BASE + 0x70064)
> > +#define DSPFW_SR_HI_SHIFT 24
> > +#define DSPFW_SR_HI_MASK (1<<24)
> > +#define DSPFW_SPRITEF_HI_SHIFT 23
> > +#define DSPFW_SPRITEF_HI_MASK (1<<23)
> > +#define DSPFW_SPRITEE_HI_SHIFT 22
> > +#define DSPFW_SPRITEE_HI_MASK (1<<22)
> > +#define DSPFW_PLANEC_HI_SHIFT 21
> > +#define DSPFW_PLANEC_HI_MASK (1<<21)
>
> It looks like bits 23:21 were removed. They are just marked as reserved now.
I see them in the CHV doc. They're for pipe C planes, so CHV only.
>
>
> > +#define DSPFW_SPRITED_HI_SHIFT 20
> > +#define DSPFW_SPRITED_HI_MASK (1<<20)
> > +#define DSPFW_SPRITEC_HI_SHIFT 16
> > +#define DSPFW_SPRITEC_HI_MASK (1<<16)
> > +#define DSPFW_PLANEB_HI_SHIFT 12
> > +#define DSPFW_PLANEB_HI_MASK (1<<12)
> > +#define DSPFW_SPRITEB_HI_SHIFT 8
> > +#define DSPFW_SPRITEB_HI_MASK (1<<8)
> > +#define DSPFW_SPRITEA_HI_SHIFT 4
> > +#define DSPFW_SPRITEA_HI_MASK (1<<4)
> > +#define DSPFW_PLANEA_HI_SHIFT 0
> > +#define DSPFW_PLANEA_HI_MASK (1<<0)
> > +#define DSPHOWM1 (VLV_DISPLAY_BASE + 0x70064)
>
> Should be 0x70068.
Nice catch. Will fix.
>
>
> > +#define DSPFW_SR_WM1_HI_SHIFT 24
> > +#define DSPFW_SR_WM1_HI_MASK (1<<24)
> > +#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
> > +#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
> > +#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
> > +#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
> > +#define DSPFW_PLANEC_WM1_HI_SHIFT 21
> > +#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
>
> Same story about 23:21 here.
>
> Everything else looks correct. With the details above
> fixed/addressed/explained: Reviewed-by: Paulo Zanoni
> <paulo.r.zanoni@intel.com>.
>
> > +#define DSPFW_SPRITED_WM1_HI_SHIFT 20
> > +#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
> > +#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
> > +#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
> > +#define DSPFW_PLANEB_WM1_HI_SHIFT 12
> > +#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
> > +#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
> > +#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
> > +#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
> > +#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
> > +#define DSPFW_PLANEA_WM1_HI_SHIFT 0
> > +#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
> >
> > /* drain latency register values*/
> > #define DRAIN_LATENCY_PRECISION_32 32
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3aa7959..dc858b5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -1360,7 +1360,7 @@ static void valleyview_update_wm(struct drm_crtc *crtc)
> > (plane_sr << DSPFW_SR_SHIFT) |
> > (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> > (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > - planea_wm);
> > + (planea_wm << DSPFW_PLANEA_SHIFT));
> > I915_WRITE(DSPFW2,
> > (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> > (cursora_wm << DSPFW_CURSORA_SHIFT));
> > @@ -1412,7 +1412,7 @@ static void g4x_update_wm(struct drm_crtc *crtc)
> > (plane_sr << DSPFW_SR_SHIFT) |
> > (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> > (planeb_wm << DSPFW_PLANEB_SHIFT) |
> > - planea_wm);
> > + (planea_wm << DSPFW_PLANEA_SHIFT));
> > I915_WRITE(DSPFW2,
> > (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
> > (cursora_wm << DSPFW_CURSORA_SHIFT));
> > @@ -1484,8 +1484,11 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
> >
> > /* 965 has limitations... */
> > I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
> > - (8 << 16) | (8 << 8) | (8 << 0));
> > - I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
> > + (8 << DSPFW_CURSORB_SHIFT) |
> > + (8 << DSPFW_PLANEB_SHIFT) |
> > + (8 << DSPFW_PLANEA_SHIFT));
> > + I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
> > + (8 << DSPFW_PLANEC_SHIFT_OLD));
> > /* update cursor SR watermark */
> > I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
> > }
> > --
> > 1.8.5.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2014-08-01 11:26 UTC|newest]
Thread overview: 109+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-27 23:03 [PATCH 00/40] CHV stuff mostly ville.syrjala
2014-06-27 23:03 ` [PATCH 01/40] drm/i915: Try to populate mem_freq for chv ville.syrjala
2014-07-12 13:27 ` Deepak S
2014-06-27 23:03 ` [PATCH 02/40] drm/i915: Use the cached min/min/rpe values in the vlv debugfs code ville.syrjala
2014-07-12 13:30 ` Deepak S
2014-07-11 14:04 ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 03/40] drm/i915: Align chv rps min/max/rpe values ville.syrjala
2014-07-12 13:46 ` Deepak S
2014-07-28 15:17 ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 04/40] drm/i915: Populate mem_freq in init_gt_powerwave() ville.syrjala
2014-06-27 23:03 ` [PATCH 05/40] drm/i915: Don't disable PPGTT for CHV based in PCI rev ville.syrjala
2014-07-12 13:48 ` Deepak S
2014-07-11 13:59 ` Daniel Vetter
2014-06-27 23:03 ` [PATCH 06/40] drm/i915: Add cdclk change support for chv ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-07-29 17:59 ` Daniel Vetter
2014-07-29 18:07 ` Jesse Barnes
2014-07-29 18:39 ` Ville Syrjälä
2014-06-27 23:03 ` [PATCH 07/40] drm/i915: Disable cdclk changes for chv until Punit is ready ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-06-27 23:03 ` [PATCH 08/40] drm/i915: Leave DPLL ref clocks on ville.syrjala
2014-07-29 16:51 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 09/40] drm/i915: Split chv_update_pll() apart ville.syrjala
2014-07-29 16:53 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 10/40] drm/i915: Call encoder->post_disable() in intel_sanitize_encoder() ville.syrjala
2014-07-11 14:46 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 11/40] drm/i915: Call intel_{dp, hdmi}_prepare for chv ville.syrjala
2014-07-29 16:54 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 12/40] drm/i915: Clarify CHV swing margin/deemph bits ville.syrjala
2014-07-29 16:55 ` Jesse Barnes
2014-07-29 19:09 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 13/40] drm/i915: Make sure hardware uses the correct swing margin/deemph bits on chv ville.syrjala
2014-06-27 23:04 ` [PATCH 14/40] drm/i915: Override display PHY TX FIFO reset master " ville.syrjala
2014-07-29 16:57 ` Jesse Barnes
2014-08-01 13:10 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 15/40] drm/i915: Clear TX FIFO reset master override bits " ville.syrjala
2014-08-01 13:23 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 16/40] drm/i915: Add chv_power_wells[] ville.syrjala
2014-07-11 14:09 ` Barbalho, Rafael
2014-07-30 11:18 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 17/40] drm/i915: Add chv cmnlane power wells ville.syrjala
2014-07-25 11:55 ` Imre Deak
2014-07-28 15:18 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 18/40] drm/i915: Kill intel_reset_dpio() ville.syrjala
2014-07-25 11:56 ` Imre Deak
2014-06-27 23:04 ` [PATCH 19/40] drm/i915: Add disp2d power well for chv ville.syrjala
2014-07-25 13:23 ` Imre Deak
2014-06-27 23:04 ` [PATCH 20/40] drm/i915: Add per-pipe power wells " ville.syrjala
2014-07-25 13:24 ` Imre Deak
2014-06-27 23:04 ` [PATCH 21/40] drm/i915: Add chv port B and C TX wells ville.syrjala
2014-07-25 13:25 ` Imre Deak
2014-06-27 23:04 ` [PATCH 22/40] drm/i915: Add chv port D " ville.syrjala
2014-07-25 13:30 ` Imre Deak
2014-07-28 9:11 ` Daniel Vetter
2014-07-28 15:19 ` Ville Syrjälä
2014-07-29 9:54 ` Imre Deak
2014-07-29 10:27 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 23/40] drm/i915: Fix drain latency precision multipler for VLV ville.syrjala
2014-07-31 15:08 ` Paulo Zanoni
2014-07-31 15:16 ` Ville Syrjälä
2014-07-31 17:05 ` Paulo Zanoni
2014-07-31 17:13 ` Ville Syrjälä
2014-07-31 18:06 ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 24/40] drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values ville.syrjala
2014-07-31 18:08 ` Paulo Zanoni
2014-08-01 12:33 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 25/40] drm/i915: Fill out the FWx watermark register defines ville.syrjala
2014-07-31 20:16 ` Paulo Zanoni
2014-08-01 11:26 ` Ville Syrjälä [this message]
2014-08-01 12:28 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 26/40] drm/i915: Parametrize VLV_DDL registers ville.syrjala
2014-07-30 20:43 ` Paulo Zanoni
2014-07-31 12:05 ` Ville Syrjälä
2014-07-31 12:11 ` [PATCH v2 " ville.syrjala
2014-06-27 23:04 ` [PATCH 27/40] drm/i915: Split a few long debug prints ville.syrjala
2014-07-29 16:59 ` Jesse Barnes
2014-06-27 23:04 ` [PATCH 28/40] drm/i915: Add cherryview_update_wm() ville.syrjala
2014-07-31 20:57 ` Paulo Zanoni
2014-08-01 11:33 ` Ville Syrjälä
2014-08-01 12:36 ` [PATCH v2 " ville.syrjala
2014-08-01 14:29 ` Paulo Zanoni
2014-06-27 23:04 ` [PATCH 29/40] drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper ville.syrjala
2014-07-29 16:59 ` Jesse Barnes
2014-07-29 18:01 ` Daniel Vetter
2014-07-30 20:23 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 30/40] drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround ville.syrjala
2014-07-11 13:30 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 31/40] drm/i916: Init chv workarounds at render ring init ville.syrjala
2014-07-30 12:35 ` Barbalho, Rafael
2014-07-30 12:48 ` Ville Syrjälä
2014-06-27 23:04 ` [PATCH 32/40] drm/i915: Hack to tie both common lanes together on chv ville.syrjala
2014-07-30 12:12 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 33/40] drm/i915: Polish the chv cmnlane resrt macros ville.syrjala
2014-07-30 12:13 ` Barbalho, Rafael
2014-06-27 23:04 ` [PATCH 34/40] drm/i915: Add DP training pattern 3 for CHV ville.syrjala
2014-07-29 17:01 ` Jesse Barnes
2014-07-29 18:04 ` Daniel Vetter
2014-07-29 18:34 ` Ville Syrjälä
2014-07-29 19:12 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 35/40] drm/i915: Fix vdd locking ville.syrjala
2014-06-27 23:04 ` [PATCH 36/40] drm/i915: Allow vdd_off when vdd is already off ville.syrjala
2014-06-27 23:04 ` [PATCH 37/40] drm/i915: Fix eDP link training when switching pipes ville.syrjala
2014-06-30 21:52 ` Jesse Barnes
2014-07-29 18:06 ` Daniel Vetter
2014-07-29 19:18 ` Ville Syrjälä
2014-07-29 19:23 ` Daniel Vetter
2014-06-27 23:04 ` [PATCH 38/40] drm/i915: Track which port is using which pipe's power sequencer ville.syrjala
2014-06-27 23:04 ` [PATCH 39/40] drm/i915: Kick the power sequencer before AUX transactions ville.syrjala
2014-06-27 23:04 ` [PATCH 40/40] drm/i915: Unstuck power sequencer when lighting up a DP port ville.syrjala
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