From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XE9IJ-0005p1-ES for qemu-devel@nongnu.org; Sun, 03 Aug 2014 23:50:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XE9ID-0002ed-DT for qemu-devel@nongnu.org; Sun, 03 Aug 2014 23:50:43 -0400 Received: from mail-yk0-x233.google.com ([2607:f8b0:4002:c07::233]:55117) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XE9ID-0002eF-7Y for qemu-devel@nongnu.org; Sun, 03 Aug 2014 23:50:37 -0400 Received: by mail-yk0-f179.google.com with SMTP id 142so3848046ykq.38 for ; Sun, 03 Aug 2014 20:50:36 -0700 (PDT) Date: Mon, 4 Aug 2014 13:48:10 +1000 From: "Edgar E. Iglesias" Message-ID: <20140804034810.GU13735@toto> References: <1402994746-8328-1-git-send-email-edgar.iglesias@gmail.com> <1402994746-8328-8-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v3 07/16] target-arm: Add HCR_EL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Peter Crosthwaite , Fabian Aggeler , QEMU Developers , Alexander Graf , Blue Swirl , John Williams , Greg Bellows , Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= , Christoffer Dall , Richard Henderson On Fri, Aug 01, 2014 at 02:29:28PM +0100, Peter Maydell wrote: > On 17 June 2014 09:45, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index 7170086..b04fb5d 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -2107,10 +2107,36 @@ static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = { > > .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0, > > .access = PL2_RW, > > .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > > + { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64, > > + .type = ARM_CP_NO_MIGRATE, > > + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, > > + .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, > > Isn't this missing the .access specifier ? Good catch, thanks. > > > REGINFO_SENTINEL > > }; > > > > +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > > +{ > > + ARMCPU *cpu = arm_env_get_cpu(env); > > + uint64_t valid_mask = HCR_MASK; > > + > > + if (!arm_feature(env, ARM_FEATURE_EL3)) { > > + valid_mask &= ~HCR_HCD; > > + } > > This is inconsistent. HCD isn't the only bit that's "RES0 if > EL3 unimplemented"; TSC is as well, for instance. > (In fact the RES0 definition means you don't actually have > to mask this out unless it's more convenient to do so.) I've added TSC. Couldn't see any others.. > > > + > > + /* Clear RES0 bits. */ > > + value &= valid_mask; > > + > > + if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_RW | HCR_PTW | HCR_DC)) { > > + tlb_flush(CPU(cpu), 1); > > Could maybe use a comment about why we need a TLB flush. I'll add one. Actually, when thinking more about it, I'm not convinced that we will need to flush when HCR_RW changes because the 32/64bit state is part of the tbflags. Cheers, Edgar