[RFH]: AMD CR intercept for lmsw/clts

[Mukesh Rathor <mukesh.rathor@oracle.com>]

Hi,

On AMD, clts/lmsw will cause "mov cr" vmexit, but unlike intel, they
can't be handled via svm_vmexit_do_cr_access and are emulated thru
handle_mmio() which is a problem for pvh because of:

handle_mmio():
..
    ASSERT(!is_pvh_vcpu(curr));

AMD CR intercepts in svm.c:
    case VMEXIT_CR0_READ ... VMEXIT_CR15_READ:
    case VMEXIT_CR0_WRITE ... VMEXIT_CR15_WRITE:
        if ( cpu_has_svm_decode && (vmcb->exitinfo1 & (1ULL << 63)) )
            svm_vmexit_do_cr_access(vmcb, regs);
        else if ( !handle_mmio() )     <==========
            hvm_inject_hw_exception(TRAP_gp_fault, 0);
    break;

Soooo, this leaves no choice but to make the ASSERT conditional
for intel only, and let handle_mmio go thru x86_emulate and let
x86_emulate fail for anything other than lmsw/clts? I was thinking
something like:

x86_emulate()
  int fail_pvh_emul = 1;
  ...
  case lmsw/clts:
     .....
     fail_pvh_emul = 0;

then
 done:
     if (fail_pvh_emul)
         rc = X86EMUL_UNHANDLEABLE;
     return rc;

Or, should I just create a new function for clts/lmsw and call it
directly from vmexit switch itself?

Can't think of any other clever way to do this... thoughts/suggestions?

thanks,
Mukesh