Re: [PATCH] perf/x86: fix load latency/precise store data source issues

[Andi Kleen <ak@linux.intel.com>]

On Tue, Aug 05, 2014 at 06:13:33AM +0200, Stephane Eranian wrote:
> 
> This patch fixes some issues introduced by Andi's 'Revamp
> PEBS' event selection patch (which is under review right now).
> 
> Most of the issues were related to the encoding of the
> data source, for PEBS events in general and load/store
> events on Haswell.
> 
> This patchd does:
>  - the default of 0 in perf_sample_data_init() was wrong. 0 is not
>   a valid value. So defined PERF_MEM_NA (not available)

Looks good.

> 
>  - On HSW, renamed your precise_store_hsw() to datala_hsw()
>    because you are actually processing both loads and stores, except
>    the load latency event which goes thru normal function

Pleae don't mix cleanups with bug fixes.

> 
>  - precise_store_data_hsw() was returning bogus data source for store
>    events. dse.mem_lvl instead of dse.val

This was already fixed in the second patch (and it wasn't introduced
by my patch):

commit 57f6c0e81f5b82b341c4c4ddd621531788c50433
Author: Andi Kleen <ak@linux.intel.com>
Date:   Fri Jul 18 17:41:48 2014 -0700

    perf, x86: Fix haswell mem hierarchy flags reporting
    
    This fixes a bug introduced with
    
    commit 722e76e60f2775c21b087ff12c5e678cf0ebcaaf
    Author: Stephane Eranian <eranian@google.com>
    Date:   Thu May 15 17:56:44 2014 +0200
    
        fix Haswell precise store data source encoding
    
    When returning early we need to return the complete value of the
    memory hierarchy, not just the mem_lvl. Otherwise any load/store/na
    flags set early get lost.
    
    Signed-off-by: Andi Kleen <ak@linux.intel.com>

-Andi