From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawn.guo@freescale.com (Shawn Guo) Date: Thu, 7 Aug 2014 11:11:36 +0800 Subject: [PATCH V2 3/3] ARM: imx6q: Add the clock route from external OSC to ESAI clock In-Reply-To: <309d5e2cb941aba7d81e2d87a8237c4ef677e45c.1407313676.git.shengjiu.wang@freescale.com> References: <309d5e2cb941aba7d81e2d87a8237c4ef677e45c.1407313676.git.shengjiu.wang@freescale.com> Message-ID: <20140807031135.GO2167@dragon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Aug 06, 2014 at 04:35:15PM +0800, Shengjiu Wang wrote: > This patch mainly adds the clock route from external 24.576MHz OSC to internal > ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an > entirely synchronous clock source against CS42888. > > [ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC, > we would get noise during the audio playback via ESAI->CS42888 even though > this generated clock's rate is equal to the external one statistically. It > might be resulted from the tiny difference between two clock source, which > might be crucial to the sensitive CODEC we use -- CS42888. > > 2, Ideally, we should use bypass mode for pll4 since we only need to get > the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't > supported. After bypass mode implement, then we can refine this patch.] I meant we should implement bypass mode first. I will give it a try. Shawn > > Expected result: > > anaclk2 0 1 24576000 > lvds2_in 0 1 24576000 > pll4_sel 0 1 24576000 > pll4_audio 0 1 786432000 > pll4_post_div 0 1 786432000 > pll4_audio_div 0 1 786432000 > esai_sel 0 1 786432000 > esai_pred 0 1 98304000 > esai_podf 0 1 24576000 > esai_extal 0 1 24576000 > > Signed-off-by: Nicolin Chen > Signed-off-by: Shengjiu Wang > --- > arch/arm/mach-imx/clk-imx6q.c | 5 +++++ > arch/arm/mach-imx/mach-imx6q.c | 28 ++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > index 330aad3..29151cb 100644 > --- a/arch/arm/mach-imx/clk-imx6q.c > +++ b/arch/arm/mach-imx/clk-imx6q.c > @@ -414,6 +414,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > > clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], "pll4_audio_div", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_PLL4_SEL], "pll4_sel", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_LVDS2_IN], "lvds2_in", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_ESAI_EXTAL], "esai_extal", NULL); > > if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || > cpu_is_imx6dl()) { > @@ -457,6 +461,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > > /* Audio-related clocks configuration */ > clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); > + clk_set_parent(clk[IMX6QDL_CLK_ESAI_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]); > > /* All existing boards with PCIe use LVDS1 */ > if (IS_ENABLED(CONFIG_PCI_IMX6)) > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c > index d51c6e9..ea24a96 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -362,6 +362,28 @@ put_node: > of_node_put(np); > } > > +#define ESAI_AUDIO_MCLK 24576000 > + > +static void __init imx6q_audio_lvds2_init(void) > +{ > + struct clk *pll4_sel, *lvds2_in, *pll4_audio_div, *esai_extal; > + > + pll4_audio_div = clk_get_sys(NULL, "pll4_audio_div"); > + pll4_sel = clk_get_sys(NULL, "pll4_sel"); > + lvds2_in = clk_get_sys(NULL, "lvds2_in"); > + esai_extal = clk_get_sys(NULL, "esai_extal"); > + if (IS_ERR(pll4_audio_div) || IS_ERR(pll4_sel) || > + IS_ERR(lvds2_in) || IS_ERR(esai_extal)) > + return; > + > + if (clk_get_rate(lvds2_in) != ESAI_AUDIO_MCLK) > + return; > + > + clk_set_parent(pll4_sel, lvds2_in); > + clk_set_rate(pll4_audio_div, 786432000); > + clk_set_rate(esai_extal, ESAI_AUDIO_MCLK); > +} > + > static struct platform_device imx6q_cpufreq_pdev = { > .name = "imx6q-cpufreq", > }; > @@ -379,6 +401,12 @@ static void __init imx6q_init_late(void) > imx6q_opp_init(); > platform_device_register(&imx6q_cpufreq_pdev); > } > + > + if (of_machine_is_compatible("fsl,imx6q-sabreauto") > + || of_machine_is_compatible("fsl,imx6dl-sabreauto")) { > + imx6q_audio_lvds2_init(); > + } > + > } > > static void __init imx6q_map_io(void) > -- > 1.7.9.5 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755105AbaHGDMK (ORCPT ); Wed, 6 Aug 2014 23:12:10 -0400 Received: from mail-bl2lp0211.outbound.protection.outlook.com ([207.46.163.211]:14994 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754724AbaHGDMI (ORCPT ); Wed, 6 Aug 2014 23:12:08 -0400 Date: Thu, 7 Aug 2014 11:11:36 +0800 From: Shawn Guo To: Shengjiu Wang CC: , , , , , , , , , Subject: Re: [PATCH V2 3/3] ARM: imx6q: Add the clock route from external OSC to ESAI clock Message-ID: <20140807031135.GO2167@dragon> References: <309d5e2cb941aba7d81e2d87a8237c4ef677e45c.1407313676.git.shengjiu.wang@freescale.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <309d5e2cb941aba7d81e2d87a8237c4ef677e45c.1407313676.git.shengjiu.wang@freescale.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50;CTRY:US;IPV:CAL;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(6009001)(51704005)(24454002)(189002)(199002)(110136001)(83072002)(87936001)(54356999)(68736004)(81342001)(33716001)(107046002)(92726001)(6806004)(106466001)(105606002)(4396001)(46406003)(76176999)(21056001)(85852003)(92566001)(44976005)(46102001)(99396002)(19580395003)(80022001)(97736001)(81542001)(83322001)(50986999)(104016003)(19580405001)(74662001)(86362001)(33656002)(23726002)(31966008)(83506001)(77982001)(79102001)(57986006)(64706001)(95666004)(85306004)(97756001)(74502001)(102836001)(76482001)(50466002)(47776003)(26826002)(84676001)(20776003)(32563001);DIR:OUT;SFP:;SCL:1;SRVR:BL2PR03MB324;H:tx30smr01.am.freescale.net;FPR:;MLV:ovrnspm;PTR:InfoDomainNonexistent;MX:1;LANG:en; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 029651C7A1 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Shawn.Guo@freescale.com; X-OriginatorOrg: freescale.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 06, 2014 at 04:35:15PM +0800, Shengjiu Wang wrote: > This patch mainly adds the clock route from external 24.576MHz OSC to internal > ESAI clock via analog clock2 PADs on the SoC and pll4 so that ESAI can get an > entirely synchronous clock source against CS42888. > > [ 1, We found if using pll4 to generate a 24.576MHz from inernal 24.0MHz OSC, > we would get noise during the audio playback via ESAI->CS42888 even though > this generated clock's rate is equal to the external one statistically. It > might be resulted from the tiny difference between two clock source, which > might be crucial to the sensitive CODEC we use -- CS42888. > > 2, Ideally, we should use bypass mode for pll4 since we only need to get > the raw rate (24.576MHz) while currently bypass mode in clk-pllv3.c isn't > supported. After bypass mode implement, then we can refine this patch.] I meant we should implement bypass mode first. I will give it a try. Shawn > > Expected result: > > anaclk2 0 1 24576000 > lvds2_in 0 1 24576000 > pll4_sel 0 1 24576000 > pll4_audio 0 1 786432000 > pll4_post_div 0 1 786432000 > pll4_audio_div 0 1 786432000 > esai_sel 0 1 786432000 > esai_pred 0 1 98304000 > esai_podf 0 1 24576000 > esai_extal 0 1 24576000 > > Signed-off-by: Nicolin Chen > Signed-off-by: Shengjiu Wang > --- > arch/arm/mach-imx/clk-imx6q.c | 5 +++++ > arch/arm/mach-imx/mach-imx6q.c | 28 ++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c > index 330aad3..29151cb 100644 > --- a/arch/arm/mach-imx/clk-imx6q.c > +++ b/arch/arm/mach-imx/clk-imx6q.c > @@ -414,6 +414,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); > > clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_PLL4_AUDIO_DIV], "pll4_audio_div", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_PLL4_SEL], "pll4_sel", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_LVDS2_IN], "lvds2_in", NULL); > + clk_register_clkdev(clk[IMX6QDL_CLK_ESAI_EXTAL], "esai_extal", NULL); > > if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || > cpu_is_imx6dl()) { > @@ -457,6 +461,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) > > /* Audio-related clocks configuration */ > clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); > + clk_set_parent(clk[IMX6QDL_CLK_ESAI_SEL], clk[IMX6QDL_CLK_PLL4_AUDIO_DIV]); > > /* All existing boards with PCIe use LVDS1 */ > if (IS_ENABLED(CONFIG_PCI_IMX6)) > diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c > index d51c6e9..ea24a96 100644 > --- a/arch/arm/mach-imx/mach-imx6q.c > +++ b/arch/arm/mach-imx/mach-imx6q.c > @@ -362,6 +362,28 @@ put_node: > of_node_put(np); > } > > +#define ESAI_AUDIO_MCLK 24576000 > + > +static void __init imx6q_audio_lvds2_init(void) > +{ > + struct clk *pll4_sel, *lvds2_in, *pll4_audio_div, *esai_extal; > + > + pll4_audio_div = clk_get_sys(NULL, "pll4_audio_div"); > + pll4_sel = clk_get_sys(NULL, "pll4_sel"); > + lvds2_in = clk_get_sys(NULL, "lvds2_in"); > + esai_extal = clk_get_sys(NULL, "esai_extal"); > + if (IS_ERR(pll4_audio_div) || IS_ERR(pll4_sel) || > + IS_ERR(lvds2_in) || IS_ERR(esai_extal)) > + return; > + > + if (clk_get_rate(lvds2_in) != ESAI_AUDIO_MCLK) > + return; > + > + clk_set_parent(pll4_sel, lvds2_in); > + clk_set_rate(pll4_audio_div, 786432000); > + clk_set_rate(esai_extal, ESAI_AUDIO_MCLK); > +} > + > static struct platform_device imx6q_cpufreq_pdev = { > .name = "imx6q-cpufreq", > }; > @@ -379,6 +401,12 @@ static void __init imx6q_init_late(void) > imx6q_opp_init(); > platform_device_register(&imx6q_cpufreq_pdev); > } > + > + if (of_machine_is_compatible("fsl,imx6q-sabreauto") > + || of_machine_is_compatible("fsl,imx6dl-sabreauto")) { > + imx6q_audio_lvds2_init(); > + } > + > } > > static void __init imx6q_map_io(void) > -- > 1.7.9.5 >