From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Continuation of future readiness series Date: Fri, 8 Aug 2014 14:55:10 +0300 Message-ID: <20140808115510.GE4193@intel.com> References: <1407497954-25230-1-git-send-email-sonika.jindal@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 15C466E08A for ; Fri, 8 Aug 2014 04:57:22 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1407497954-25230-1-git-send-email-sonika.jindal@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: sonika.jindal@intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 08, 2014 at 05:09:14PM +0530, sonika.jindal@intel.com wrote: > From: Sonika Jindal > = > Removing the check for HAS_PCH_SPLIT, it looks redundant here. Anyways al= l the > platforms are checked separately. > = > Signed-off-by: Sonika Jindal > --- > drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++------------= ------ > 1 file changed, 19 insertions(+), 21 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 89e0ac5..5a3e239 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -12421,27 +12421,25 @@ static void intel_init_display(struct drm_devic= e *dev) > dev_priv->display.get_display_clock_speed =3D > i830_get_display_clock_speed; > = > - if (HAS_PCH_SPLIT(dev)) { > - if (IS_GEN5(dev)) { > - dev_priv->display.fdi_link_train =3D ironlake_fdi_link_train; > - dev_priv->display.write_eld =3D ironlake_write_eld; > - } else if (IS_GEN6(dev)) { > - dev_priv->display.fdi_link_train =3D gen6_fdi_link_train; > - dev_priv->display.write_eld =3D ironlake_write_eld; > - dev_priv->display.modeset_global_resources =3D > - snb_modeset_global_resources; > - } else if (IS_IVYBRIDGE(dev)) { > - /* FIXME: detect B0+ stepping and use auto training */ > - dev_priv->display.fdi_link_train =3D ivb_manual_fdi_link_train; > - dev_priv->display.write_eld =3D ironlake_write_eld; > - dev_priv->display.modeset_global_resources =3D > - ivb_modeset_global_resources; > - } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { > - dev_priv->display.fdi_link_train =3D hsw_fdi_link_train; > - dev_priv->display.write_eld =3D haswell_write_eld; > - dev_priv->display.modeset_global_resources =3D > - haswell_modeset_global_resources; > - } > + if (IS_GEN5(dev)) { > + dev_priv->display.fdi_link_train =3D ironlake_fdi_link_train; > + dev_priv->display.write_eld =3D ironlake_write_eld; > + } else if (IS_GEN6(dev)) { > + dev_priv->display.fdi_link_train =3D gen6_fdi_link_train; > + dev_priv->display.write_eld =3D ironlake_write_eld; > + dev_priv->display.modeset_global_resources =3D > + snb_modeset_global_resources; > + } else if (IS_IVYBRIDGE(dev)) { > + /* FIXME: detect B0+ stepping and use auto training */ > + dev_priv->display.fdi_link_train =3D ivb_manual_fdi_link_train; > + dev_priv->display.write_eld =3D ironlake_write_eld; > + dev_priv->display.modeset_global_resources =3D > + ivb_modeset_global_resources; > + } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { > + dev_priv->display.fdi_link_train =3D hsw_fdi_link_train; > + dev_priv->display.write_eld =3D haswell_write_eld; > + dev_priv->display.modeset_global_resources =3D > + haswell_modeset_global_resources; Maybe shuffle these around a bit while you're at it so that the checks would be roughly in gen order. > } else if (IS_G4X(dev)) { > dev_priv->display.write_eld =3D g4x_write_eld; > } else if (IS_VALLEYVIEW(dev)) { > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC