Re: [Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Mon, Aug 18, 2014 at 12:57:43PM +1000, Peter Crosthwaite wrote:
> On Mon, Aug 18, 2014 at 12:18 PM, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > On Sun, Aug 17, 2014 at 06:59:59PM -0700, Peter Crosthwaite wrote:
> >> Caches are 16 bytes in A9. Self identify in CCSIDR accordingly.
> >
> > Hi,
> >
> > This is a bit confusing, caches are not 16bytes on the a9, they are configurable.
> 
> Sorry my bad. Should read "cache-line" and "32-bytes". Will fix in v2.
> I agree about about the configurability of the actual cache size but
> not touching that this patch.
> 
> > Cache lines are 32 bytes. The reported associativity doesn't match
> > either.
> 
> For 16KB caches (as the comment in the code indicates),
> > I think you want the lower bits to be fe01c.
> 
> Splitting that out, associativity = 3 (+1 = 4 for a9 4x assoc caching)
> which is correct. Will update that next spin. But line size field = 4
> which would correspond to line size of 256B.
> 
> I think line size needs to be 1 as in this patch but the other fields
> need tweaking.
> 
> Adding in your assoc fix though we should now have 0x19. in lower
> fields. Then num-sets =
> 
> 16k / 4 assoc / 32 line sz = 128 so add in 0xfe000.
> 
> I think the magic number is 0xfe019.

Yes, agreed.

Cheers,
Edgar