From: Christoffer Dall <christoffer.dall@linaro.org>
To: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/3] arm_gic: Do not force PPIs to edge-triggered mode
Date: Mon, 18 Aug 2014 14:48:15 +0200 [thread overview]
Message-ID: <20140818124815.GD19635@cbox> (raw)
In-Reply-To: <1408218501-22326-4-git-send-email-adam@os.inf.tu-dresden.de>
On Sat, Aug 16, 2014 at 09:48:21PM +0200, Adam Lackorzynski wrote:
> Only SGIs must be WI, done by forcing them to their default
> (edge-triggered).
>
> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
> ---
> hw/intc/arm_gic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index e546647..55019c9 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -558,7 +558,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
> irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
> if (irq >= s->num_irq)
> goto bad_reg;
> - if (irq < GIC_INTERNAL)
> + if (irq < GIC_NR_SGIS)
> value |= 0xaa;
> for (i = 0; i < 4; i++) {
> if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
> --
> 2.1.0.rc1
>
where do we ensure that the SGIs are actually configured as
edge-triggered when creating the gic?
-Christoffer
next prev parent reply other threads:[~2014-08-18 12:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-16 19:48 [Qemu-devel] [PATCH 0/3] arm_gic: Improve handling of GICD_ICFGR Adam Lackorzynski
2014-08-16 19:48 ` [Qemu-devel] [PATCH 1/3] arm_gic: Fix read " Adam Lackorzynski
2014-08-16 19:48 ` [Qemu-devel] [PATCH 2/3] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs Adam Lackorzynski
2014-08-18 12:46 ` Christoffer Dall
2014-08-16 19:48 ` [Qemu-devel] [PATCH 3/3] arm_gic: Do not force PPIs to edge-triggered mode Adam Lackorzynski
2014-08-18 12:48 ` Christoffer Dall [this message]
2014-08-18 12:52 ` Adam Lackorzynski
2014-08-18 13:01 ` Christoffer Dall
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