From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH 2/2] drm/i915: improve assert_panel_unlocked
Date: Thu, 21 Aug 2014 15:06:26 +0300
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Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
non-LVDS. Also don't pretend it works for DDI. There's still work to do
to get this right for eDP on PCH platforms, but this is a start.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

So I wanted to quickly fix assert_panel_unlocked, but for such a short
piece of code it's too involved to _quickly_ get right across all
platforms. I think this is a worthwhile improvement though.
---
 drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fe1d00dc9ef5..d6b48496d7f4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1193,17 +1193,33 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 				  enum pipe pipe)
 {
-	int pp_reg, lvds_reg;
+	struct drm_device *dev = dev_priv->dev;
+	int pp_reg;
 	u32 val;
 	enum pipe panel_pipe = PIPE_A;
 	bool locked = true;
 
-	if (HAS_PCH_SPLIT(dev_priv->dev)) {
+	if (HAS_DDI(dev)) {
+		/* XXX: this neither works nor gets called for DDI */
+		return;
+	} else if (HAS_PCH_SPLIT(dev)) {
+		u32 port_sel;
+
 		pp_reg = PCH_PP_CONTROL;
-		lvds_reg = PCH_LVDS;
+		port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
+
+		if (port_sel == PANEL_PORT_SELECT_LVDS &&
+		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
+			panel_pipe = PIPE_B;
+		/* XXX: else fix for eDP */
+	} else if (IS_VALLEYVIEW(dev)) {
+		/* presumably write lock depends on pipe, not port select */
+		pp_reg = VLV_PIPE_PP_CONTROL(pipe);
+		panel_pipe = pipe;
 	} else {
 		pp_reg = PP_CONTROL;
-		lvds_reg = LVDS;
+		if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
+			panel_pipe = PIPE_B;
 	}
 
 	val = I915_READ(pp_reg);
@@ -1211,9 +1227,6 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
 		locked = false;
 
-	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
-		panel_pipe = PIPE_B;
-
 	WARN(panel_pipe == pipe && locked,
 	     "panel assertion failure, pipe %c regs locked\n",
 	     pipe_name(pipe));
-- 
1.9.1

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH 1/2] drm/i915: fix panel unlock register mask
Date: Thu, 21 Aug 2014 15:06:25 +0300
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Use the correct mask for the unlock bits. In theory this could have lead
to incorrect asserts but this is unlikely in practise.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0b327ebb2d9e..fe1d00dc9ef5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1208,7 +1208,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
 
 	val = I915_READ(pp_reg);
 	if (!(val & PANEL_POWER_ON) ||
-	    ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
+	    ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
 		locked = false;
 
 	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
-- 
1.9.1

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Paulo Zanoni <przanoni@gmail.com>
Subject: Re: [PATCH 1/2] drm/i915: fix panel unlock register mask
Date: Thu, 21 Aug 2014 10:36:53 -0300
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2014-08-21 9:06 GMT-03:00 Jani Nikula <jani.nikula@intel.com>:
> Use the correct mask for the unlock bits. In theory this could have lead
> to incorrect asserts but this is unlikely in practise.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0b327ebb2d9e..fe1d00dc9ef5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1208,7 +1208,7 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>
>         val = I915_READ(pp_reg);
>         if (!(val & PANEL_POWER_ON) ||
> -           ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
> +           ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
>                 locked = false;
>
>         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Paulo Zanoni

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 1/2] drm/i915: fix panel unlock register mask
Date: Thu, 21 Aug 2014 16:39:00 +0300
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On Thu, Aug 21, 2014 at 03:06:25PM +0300, Jani Nikula wrote:
> Use the correct mask for the unlock bits. In theory this could have lead
> to incorrect asserts but this is unlikely in practise.
> =

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/=
intel_display.c
> index 0b327ebb2d9e..fe1d00dc9ef5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1208,7 +1208,7 @@ static void assert_panel_unlocked(struct drm_i915_p=
rivate *dev_priv,
>  =

>  	val =3D I915_READ(pp_reg);
>  	if (!(val & PANEL_POWER_ON) ||
> -	    ((val & PANEL_UNLOCK_REGS) =3D=3D PANEL_UNLOCK_REGS))
> +	    ((val & PANEL_UNLOCK_MASK) =3D=3D PANEL_UNLOCK_REGS))
>  		locked =3D false;
>  =

>  	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
> -- =

> 1.9.1
> =

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- =

Ville Syrj=E4l=E4
Intel OTC

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/2] drm/i915: improve assert_panel_unlocked
Date: Thu, 21 Aug 2014 17:56:40 +0300
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On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote:
> Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
> non-LVDS. Also don't pretend it works for DDI. There's still work to do
> to get this right for eDP on PCH platforms, but this is a start.
> =

> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> =

> ---
> =

> So I wanted to quickly fix assert_panel_unlocked, but for such a short
> piece of code it's too involved to _quickly_ get right across all
> platforms. I think this is a worthwhile improvement though.
> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++-------
>  1 file changed, 20 insertions(+), 7 deletions(-)
> =

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/=
intel_display.c
> index fe1d00dc9ef5..d6b48496d7f4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1193,17 +1193,33 @@ void assert_fdi_rx_pll(struct drm_i915_private *d=
ev_priv,
>  static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
>  				  enum pipe pipe)
>  {
> -	int pp_reg, lvds_reg;
> +	struct drm_device *dev =3D dev_priv->dev;
> +	int pp_reg;
>  	u32 val;
>  	enum pipe panel_pipe =3D PIPE_A;
>  	bool locked =3D true;
>  =

> -	if (HAS_PCH_SPLIT(dev_priv->dev)) {
> +	if (HAS_DDI(dev)) {
> +		/* XXX: this neither works nor gets called for DDI */

Not sure why the XXX here. Seems to me there's nothing to fix here for
DDI. Maybe just make that a WARN_ON(HAS_DDI()) or just remove the check
entirely.

> +		return;
> +	} else if (HAS_PCH_SPLIT(dev)) {
> +		u32 port_sel;
> +
>  		pp_reg =3D PCH_PP_CONTROL;
> -		lvds_reg =3D PCH_LVDS;
> +		port_sel =3D I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
> +
> +		if (port_sel =3D=3D PANEL_PORT_SELECT_LVDS &&
> +		    I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
> +			panel_pipe =3D PIPE_B;
> +		/* XXX: else fix for eDP */
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		/* presumably write lock depends on pipe, not port select */

Hmm. This is a good question. Needs a bit if testing I suppose. In the
worst case it somehow gets tied in with how the power sequencer gets locked
to the port. For that we'd probably just have to check both power sequencers
here and complain if either has the registers locked. Or maybe we should
just do that anyway because it's such a simple solution? But we could
do that simply by calling assert_panel_unlocked() twice (once for each pipe)
from VLV specific code, so this patch seems to be exactly what we need as
a first step.

Apart from the XXX in the comment:
Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>

> +		pp_reg =3D VLV_PIPE_PP_CONTROL(pipe);
> +		panel_pipe =3D pipe;
>  	} else {
>  		pp_reg =3D PP_CONTROL;
> -		lvds_reg =3D LVDS;
> +		if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
> +			panel_pipe =3D PIPE_B;
>  	}
>  =

>  	val =3D I915_READ(pp_reg);
> @@ -1211,9 +1227,6 @@ static void assert_panel_unlocked(struct drm_i915_p=
rivate *dev_priv,
>  	    ((val & PANEL_UNLOCK_MASK) =3D=3D PANEL_UNLOCK_REGS))
>  		locked =3D false;
>  =

> -	if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
> -		panel_pipe =3D PIPE_B;
> -
>  	WARN(panel_pipe =3D=3D pipe && locked,
>  	     "panel assertion failure, pipe %c regs locked\n",
>  	     pipe_name(pipe));
> -- =

> 1.9.1
> =

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- =

Ville Syrj=E4l=E4
Intel OTC

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Paulo Zanoni <przanoni@gmail.com>
Subject: Re: [PATCH 2/2] drm/i915: improve assert_panel_unlocked
Date: Thu, 21 Aug 2014 12:01:07 -0300
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MjAxNC0wOC0yMSAxMTo1NiBHTVQtMDM6MDAgVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxh
QGxpbnV4LmludGVsLmNvbT46Cj4gT24gVGh1LCBBdWcgMjEsIDIwMTQgYXQgMDM6MDY6MjZQTSAr
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dCBwcmV0ZW5kIGl0IHdvcmtzIGZvciBEREkuIFRoZXJlJ3Mgc3RpbGwgd29yayB0byBkbwo+PiB0
byBnZXQgdGhpcyByaWdodCBmb3IgZURQIG9uIFBDSCBwbGF0Zm9ybXMsIGJ1dCB0aGlzIGlzIGEg
c3RhcnQuCj4+Cj4+IFNpZ25lZC1vZmYtYnk6IEphbmkgTmlrdWxhIDxqYW5pLm5pa3VsYUBpbnRl
bC5jb20+Cj4+Cj4+IC0tLQo+Pgo+PiBTbyBJIHdhbnRlZCB0byBxdWlja2x5IGZpeCBhc3NlcnRf
cGFuZWxfdW5sb2NrZWQsIGJ1dCBmb3Igc3VjaCBhIHNob3J0Cj4+IHBpZWNlIG9mIGNvZGUgaXQn
cyB0b28gaW52b2x2ZWQgdG8gX3F1aWNrbHlfIGdldCByaWdodCBhY3Jvc3MgYWxsCj4+IHBsYXRm
b3Jtcy4gSSB0aGluayB0aGlzIGlzIGEgd29ydGh3aGlsZSBpbXByb3ZlbWVudCB0aG91Z2guCj4+
IC0tLQo+PiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jIHwgMjcgKysrKysr
KysrKysrKysrKysrKystLS0tLS0tCj4+ICAxIGZpbGUgY2hhbmdlZCwgMjAgaW5zZXJ0aW9ucygr
KSwgNyBkZWxldGlvbnMoLSkKPj4KPj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1
L2ludGVsX2Rpc3BsYXkuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+
PiBpbmRleCBmZTFkMDBkYzllZjUuLmQ2YjQ4NDk2ZDdmNCAxMDA2NDQKPj4gLS0tIGEvZHJpdmVy
cy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jCj4+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9p
OTE1L2ludGVsX2Rpc3BsYXkuYwo+PiBAQCAtMTE5MywxNyArMTE5MywzMyBAQCB2b2lkIGFzc2Vy
dF9mZGlfcnhfcGxsKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKPj4gIHN0YXRp
YyB2b2lkIGFzc2VydF9wYW5lbF91bmxvY2tlZChzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2
X3ByaXYsCj4+ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZW51bSBwaXBlIHBpcGUp
Cj4+ICB7Cj4+IC0gICAgIGludCBwcF9yZWcsIGx2ZHNfcmVnOwo+PiArICAgICBzdHJ1Y3QgZHJt
X2RldmljZSAqZGV2ID0gZGV2X3ByaXYtPmRldjsKPj4gKyAgICAgaW50IHBwX3JlZzsKPj4gICAg
ICAgdTMyIHZhbDsKPj4gICAgICAgZW51bSBwaXBlIHBhbmVsX3BpcGUgPSBQSVBFX0E7Cj4+ICAg
ICAgIGJvb2wgbG9ja2VkID0gdHJ1ZTsKPj4KPj4gLSAgICAgaWYgKEhBU19QQ0hfU1BMSVQoZGV2
X3ByaXYtPmRldikpIHsKPj4gKyAgICAgaWYgKEhBU19EREkoZGV2KSkgewo+PiArICAgICAgICAg
ICAgIC8qIFhYWDogdGhpcyBuZWl0aGVyIHdvcmtzIG5vciBnZXRzIGNhbGxlZCBmb3IgRERJICov
Cj4KPiBOb3Qgc3VyZSB3aHkgdGhlIFhYWCBoZXJlLiBTZWVtcyB0byBtZSB0aGVyZSdzIG5vdGhp
bmcgdG8gZml4IGhlcmUgZm9yCj4gRERJLiBNYXliZSBqdXN0IG1ha2UgdGhhdCBhIFdBUk5fT04o
SEFTX0RESSgpKSBvciBqdXN0IHJlbW92ZSB0aGUgY2hlY2sKPiBlbnRpcmVseS4KCkFzIGZhciBh
cyBJIHJlbWVtYmVyLCB0aGUgImFiY2QiIHN0dWZmIGlzIG5vdCBldmVuIHVzZWQvbmVlZGVkIG9u
IERESS4KQnV0IHRoaXMgaXMganVzdCB3aGF0IG15IG1lbW9yeSB0ZWxscyBtZSwgaXQgbWF5IGJl
IHdyb25nLiBTb21lb25lCm5lZWRzIHRvIGRvdWJsZS1jaGVjay4KCj4KPj4gKyAgICAgICAgICAg
ICByZXR1cm47Cj4+ICsgICAgIH0gZWxzZSBpZiAoSEFTX1BDSF9TUExJVChkZXYpKSB7Cj4+ICsg
ICAgICAgICAgICAgdTMyIHBvcnRfc2VsOwo+PiArCj4+ICAgICAgICAgICAgICAgcHBfcmVnID0g
UENIX1BQX0NPTlRST0w7Cj4+IC0gICAgICAgICAgICAgbHZkc19yZWcgPSBQQ0hfTFZEUzsKPj4g
KyAgICAgICAgICAgICBwb3J0X3NlbCA9IEk5MTVfUkVBRChQQ0hfUFBfT05fREVMQVlTKSAmIFBB
TkVMX1BPUlRfU0VMRUNUX01BU0s7Cj4+ICsKPj4gKyAgICAgICAgICAgICBpZiAocG9ydF9zZWwg
PT0gUEFORUxfUE9SVF9TRUxFQ1RfTFZEUyAmJgo+PiArICAgICAgICAgICAgICAgICBJOTE1X1JF
QUQoUENIX0xWRFMpICYgTFZEU19QSVBFQl9TRUxFQ1QpCj4+ICsgICAgICAgICAgICAgICAgICAg
ICBwYW5lbF9waXBlID0gUElQRV9COwo+PiArICAgICAgICAgICAgIC8qIFhYWDogZWxzZSBmaXgg
Zm9yIGVEUCAqLwo+PiArICAgICB9IGVsc2UgaWYgKElTX1ZBTExFWVZJRVcoZGV2KSkgewo+PiAr
ICAgICAgICAgICAgIC8qIHByZXN1bWFibHkgd3JpdGUgbG9jayBkZXBlbmRzIG9uIHBpcGUsIG5v
dCBwb3J0IHNlbGVjdCAqLwo+Cj4gSG1tLiBUaGlzIGlzIGEgZ29vZCBxdWVzdGlvbi4gTmVlZHMg
YSBiaXQgaWYgdGVzdGluZyBJIHN1cHBvc2UuIEluIHRoZQo+IHdvcnN0IGNhc2UgaXQgc29tZWhv
dyBnZXRzIHRpZWQgaW4gd2l0aCBob3cgdGhlIHBvd2VyIHNlcXVlbmNlciBnZXRzIGxvY2tlZAo+
IHRvIHRoZSBwb3J0LiBGb3IgdGhhdCB3ZSdkIHByb2JhYmx5IGp1c3QgaGF2ZSB0byBjaGVjayBi
b3RoIHBvd2VyIHNlcXVlbmNlcnMKPiBoZXJlIGFuZCBjb21wbGFpbiBpZiBlaXRoZXIgaGFzIHRo
ZSByZWdpc3RlcnMgbG9ja2VkLiBPciBtYXliZSB3ZSBzaG91bGQKPiBqdXN0IGRvIHRoYXQgYW55
d2F5IGJlY2F1c2UgaXQncyBzdWNoIGEgc2ltcGxlIHNvbHV0aW9uPyBCdXQgd2UgY291bGQKPiBk
byB0aGF0IHNpbXBseSBieSBjYWxsaW5nIGFzc2VydF9wYW5lbF91bmxvY2tlZCgpIHR3aWNlIChv
bmNlIGZvciBlYWNoIHBpcGUpCj4gZnJvbSBWTFYgc3BlY2lmaWMgY29kZSwgc28gdGhpcyBwYXRj
aCBzZWVtcyB0byBiZSBleGFjdGx5IHdoYXQgd2UgbmVlZCBhcwo+IGEgZmlyc3Qgc3RlcC4KPgo+
IEFwYXJ0IGZyb20gdGhlIFhYWCBpbiB0aGUgY29tbWVudDoKPiBSZXZpZXdlZC1ieTogVmlsbGUg
U3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4KPgo+PiArICAgICAgICAg
ICAgIHBwX3JlZyA9IFZMVl9QSVBFX1BQX0NPTlRST0wocGlwZSk7Cj4+ICsgICAgICAgICAgICAg
cGFuZWxfcGlwZSA9IHBpcGU7Cj4+ICAgICAgIH0gZWxzZSB7Cj4+ICAgICAgICAgICAgICAgcHBf
cmVnID0gUFBfQ09OVFJPTDsKPj4gLSAgICAgICAgICAgICBsdmRzX3JlZyA9IExWRFM7Cj4+ICsg
ICAgICAgICAgICAgaWYgKEk5MTVfUkVBRChMVkRTKSAmIExWRFNfUElQRUJfU0VMRUNUKQo+PiAr
ICAgICAgICAgICAgICAgICAgICAgcGFuZWxfcGlwZSA9IFBJUEVfQjsKPj4gICAgICAgfQo+Pgo+
PiAgICAgICB2YWwgPSBJOTE1X1JFQUQocHBfcmVnKTsKPj4gQEAgLTEyMTEsOSArMTIyNyw2IEBA
IHN0YXRpYyB2b2lkIGFzc2VydF9wYW5lbF91bmxvY2tlZChzdHJ1Y3QgZHJtX2k5MTVfcHJpdmF0
ZSAqZGV2X3ByaXYsCj4+ICAgICAgICAgICAoKHZhbCAmIFBBTkVMX1VOTE9DS19NQVNLKSA9PSBQ
QU5FTF9VTkxPQ0tfUkVHUykpCj4+ICAgICAgICAgICAgICAgbG9ja2VkID0gZmFsc2U7Cj4+Cj4+
IC0gICAgIGlmIChJOTE1X1JFQUQobHZkc19yZWcpICYgTFZEU19QSVBFQl9TRUxFQ1QpCj4+IC0g
ICAgICAgICAgICAgcGFuZWxfcGlwZSA9IFBJUEVfQjsKPj4gLQo+PiAgICAgICBXQVJOKHBhbmVs
X3BpcGUgPT0gcGlwZSAmJiBsb2NrZWQsCj4+ICAgICAgICAgICAgInBhbmVsIGFzc2VydGlvbiBm
YWlsdXJlLCBwaXBlICVjIHJlZ3MgbG9ja2VkXG4iLAo+PiAgICAgICAgICAgIHBpcGVfbmFtZShw
aXBlKSk7Cj4+IC0tCj4+IDEuOS4xCj4+Cj4+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fCj4+IEludGVsLWdmeCBtYWlsaW5nIGxpc3QKPj4gSW50ZWwtZ2Z4
QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwo+PiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h
aWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cj4KPiAtLQo+IFZpbGxlIFN5cmrDpGzDpAo+IEludGVs
IE9UQwo+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4g
SW50ZWwtZ2Z4IG1haWxpbmcgbGlzdAo+IEludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcK
PiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4
CgoKCi0tIApQYXVsbyBaYW5vbmkKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRl
c2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9p
bnRlbC1nZngK

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 2/2] drm/i915: improve assert_panel_unlocked
Date: Fri, 22 Aug 2014 11:00:15 +0300
Message-ID: <20140822080015.GQ4193@intel.com>
References: <1408622786-19318-1-git-send-email-jani.nikula@intel.com>
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On Thu, Aug 21, 2014 at 12:01:07PM -0300, Paulo Zanoni wrote:
> 2014-08-21 11:56 GMT-03:00 Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.c=
om>:
> > On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote:
> >> Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
> >> non-LVDS. Also don't pretend it works for DDI. There's still work to do
> >> to get this right for eDP on PCH platforms, but this is a start.
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >>
> >> ---
> >>
> >> So I wanted to quickly fix assert_panel_unlocked, but for such a short
> >> piece of code it's too involved to _quickly_ get right across all
> >> platforms. I think this is a worthwhile improvement though.
> >> ---
> >>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++-------
> >>  1 file changed, 20 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i9=
15/intel_display.c
> >> index fe1d00dc9ef5..d6b48496d7f4 100644
> >> --- a/drivers/gpu/drm/i915/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/intel_display.c
> >> @@ -1193,17 +1193,33 @@ void assert_fdi_rx_pll(struct drm_i915_private=
 *dev_priv,
> >>  static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> >>                                 enum pipe pipe)
> >>  {
> >> -     int pp_reg, lvds_reg;
> >> +     struct drm_device *dev =3D dev_priv->dev;
> >> +     int pp_reg;
> >>       u32 val;
> >>       enum pipe panel_pipe =3D PIPE_A;
> >>       bool locked =3D true;
> >>
> >> -     if (HAS_PCH_SPLIT(dev_priv->dev)) {
> >> +     if (HAS_DDI(dev)) {
> >> +             /* XXX: this neither works nor gets called for DDI */
> >
> > Not sure why the XXX here. Seems to me there's nothing to fix here for
> > DDI. Maybe just make that a WARN_ON(HAS_DDI()) or just remove the check
> > entirely.
> =

> As far as I remember, the "abcd" stuff is not even used/needed on DDI.
> But this is just what my memory tells me, it may be wrong. Someone
> needs to double-check.

Bspec just says "spare" for those bits.

> =

> >
> >> +             return;
> >> +     } else if (HAS_PCH_SPLIT(dev)) {
> >> +             u32 port_sel;
> >> +
> >>               pp_reg =3D PCH_PP_CONTROL;
> >> -             lvds_reg =3D PCH_LVDS;
> >> +             port_sel =3D I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SE=
LECT_MASK;
> >> +
> >> +             if (port_sel =3D=3D PANEL_PORT_SELECT_LVDS &&
> >> +                 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
> >> +                     panel_pipe =3D PIPE_B;
> >> +             /* XXX: else fix for eDP */
> >> +     } else if (IS_VALLEYVIEW(dev)) {
> >> +             /* presumably write lock depends on pipe, not port selec=
t */
> >
> > Hmm. This is a good question. Needs a bit if testing I suppose. In the
> > worst case it somehow gets tied in with how the power sequencer gets lo=
cked
> > to the port. For that we'd probably just have to check both power seque=
ncers
> > here and complain if either has the registers locked. Or maybe we should
> > just do that anyway because it's such a simple solution? But we could
> > do that simply by calling assert_panel_unlocked() twice (once for each =
pipe)
> > from VLV specific code, so this patch seems to be exactly what we need =
as
> > a first step.
> >
> > Apart from the XXX in the comment:
> > Reviewed-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> >
> >> +             pp_reg =3D VLV_PIPE_PP_CONTROL(pipe);
> >> +             panel_pipe =3D pipe;
> >>       } else {
> >>               pp_reg =3D PP_CONTROL;
> >> -             lvds_reg =3D LVDS;
> >> +             if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
> >> +                     panel_pipe =3D PIPE_B;
> >>       }
> >>
> >>       val =3D I915_READ(pp_reg);
> >> @@ -1211,9 +1227,6 @@ static void assert_panel_unlocked(struct drm_i91=
5_private *dev_priv,
> >>           ((val & PANEL_UNLOCK_MASK) =3D=3D PANEL_UNLOCK_REGS))
> >>               locked =3D false;
> >>
> >> -     if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
> >> -             panel_pipe =3D PIPE_B;
> >> -
> >>       WARN(panel_pipe =3D=3D pipe && locked,
> >>            "panel assertion failure, pipe %c regs locked\n",
> >>            pipe_name(pipe));
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> Intel-gfx mailing list
> >> Intel-gfx@lists.freedesktop.org
> >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Ville Syrj=E4l=E4
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> =

> =

> =

> -- =

> Paulo Zanoni

-- =

Ville Syrj=E4l=E4
Intel OTC

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 2/2] drm/i915: improve assert_panel_unlocked
Date: Fri, 22 Aug 2014 15:04:13 +0300
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Rml4IGFzc2VydF9wYW5lbF91bmxvY2tlZCBmb3Igdmx2L2NodiwgYW5kIGltcHJvdmUgaXQgYSBi
aXQgZm9yCm5vbi1MVkRTLiBBbHNvIGRvbid0IHByZXRlbmQgaXQgd29ya3MgZm9yIERESS4gVGhl
cmUncyBzdGlsbCB3b3JrIHRvIGRvCnRvIGdldCB0aGlzIHJpZ2h0IGZvciBlRFAgb24gUENIIHBs
YXRmb3JtcywgYnV0IHRoaXMgaXMgYSBzdGFydC4KCnYyOiBXQVJOX09OKEhBU19EREkpCgpSZXZp
ZXdlZC1ieTogVmlsbGUgU3lyasOkbMOkIDx2aWxsZS5zeXJqYWxhQGxpbnV4LmludGVsLmNvbT4K
U2lnbmVkLW9mZi1ieTogSmFuaSBOaWt1bGEgPGphbmkubmlrdWxhQGludGVsLmNvbT4KLS0tCiBk
cml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kaXNwbGF5LmMgfCAyNyArKysrKysrKysrKysrKysr
KysrKy0tLS0tLS0KIDEgZmlsZSBjaGFuZ2VkLCAyMCBpbnNlcnRpb25zKCspLCA3IGRlbGV0aW9u
cygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYyBi
L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwppbmRleCBmZTFkMDBkYzllZjUu
LjUxYjRjZDI5ZjkzMiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlz
cGxheS5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwpAQCAtMTE5
MywxNyArMTE5MywzMyBAQCB2b2lkIGFzc2VydF9mZGlfcnhfcGxsKHN0cnVjdCBkcm1faTkxNV9w
cml2YXRlICpkZXZfcHJpdiwKIHN0YXRpYyB2b2lkIGFzc2VydF9wYW5lbF91bmxvY2tlZChzdHJ1
Y3QgZHJtX2k5MTVfcHJpdmF0ZSAqZGV2X3ByaXYsCiAJCQkJICBlbnVtIHBpcGUgcGlwZSkKIHsK
LQlpbnQgcHBfcmVnLCBsdmRzX3JlZzsKKwlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gZGV2X3By
aXYtPmRldjsKKwlpbnQgcHBfcmVnOwogCXUzMiB2YWw7CiAJZW51bSBwaXBlIHBhbmVsX3BpcGUg
PSBQSVBFX0E7CiAJYm9vbCBsb2NrZWQgPSB0cnVlOwogCi0JaWYgKEhBU19QQ0hfU1BMSVQoZGV2
X3ByaXYtPmRldikpIHsKKwlpZiAoV0FSTl9PTihIQVNfRERJKGRldikpKQorCQlyZXR1cm47CisK
KwlpZiAoSEFTX1BDSF9TUExJVChkZXYpKSB7CisJCXUzMiBwb3J0X3NlbDsKKwogCQlwcF9yZWcg
PSBQQ0hfUFBfQ09OVFJPTDsKLQkJbHZkc19yZWcgPSBQQ0hfTFZEUzsKKwkJcG9ydF9zZWwgPSBJ
OTE1X1JFQUQoUENIX1BQX09OX0RFTEFZUykgJiBQQU5FTF9QT1JUX1NFTEVDVF9NQVNLOworCisJ
CWlmIChwb3J0X3NlbCA9PSBQQU5FTF9QT1JUX1NFTEVDVF9MVkRTICYmCisJCSAgICBJOTE1X1JF
QUQoUENIX0xWRFMpICYgTFZEU19QSVBFQl9TRUxFQ1QpCisJCQlwYW5lbF9waXBlID0gUElQRV9C
OworCQkvKiBYWFg6IGVsc2UgZml4IGZvciBlRFAgKi8KKwl9IGVsc2UgaWYgKElTX1ZBTExFWVZJ
RVcoZGV2KSkgeworCQkvKiBwcmVzdW1hYmx5IHdyaXRlIGxvY2sgZGVwZW5kcyBvbiBwaXBlLCBu
b3QgcG9ydCBzZWxlY3QgKi8KKwkJcHBfcmVnID0gVkxWX1BJUEVfUFBfQ09OVFJPTChwaXBlKTsK
KwkJcGFuZWxfcGlwZSA9IHBpcGU7CiAJfSBlbHNlIHsKIAkJcHBfcmVnID0gUFBfQ09OVFJPTDsK
LQkJbHZkc19yZWcgPSBMVkRTOworCQlpZiAoSTkxNV9SRUFEKExWRFMpICYgTFZEU19QSVBFQl9T
RUxFQ1QpCisJCQlwYW5lbF9waXBlID0gUElQRV9COwogCX0KIAogCXZhbCA9IEk5MTVfUkVBRChw
cF9yZWcpOwpAQCAtMTIxMSw5ICsxMjI3LDYgQEAgc3RhdGljIHZvaWQgYXNzZXJ0X3BhbmVsX3Vu
bG9ja2VkKHN0cnVjdCBkcm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwKIAkgICAgKCh2YWwgJiBQ
QU5FTF9VTkxPQ0tfTUFTSykgPT0gUEFORUxfVU5MT0NLX1JFR1MpKQogCQlsb2NrZWQgPSBmYWxz
ZTsKIAotCWlmIChJOTE1X1JFQUQobHZkc19yZWcpICYgTFZEU19QSVBFQl9TRUxFQ1QpCi0JCXBh
bmVsX3BpcGUgPSBQSVBFX0I7Ci0KIAlXQVJOKHBhbmVsX3BpcGUgPT0gcGlwZSAmJiBsb2NrZWQs
CiAJICAgICAicGFuZWwgYXNzZXJ0aW9uIGZhaWx1cmUsIHBpcGUgJWMgcmVncyBsb2NrZWRcbiIs
CiAJICAgICBwaXBlX25hbWUocGlwZSkpOwotLSAKMS45LjEKCl9fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwt
Z2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21h
aWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==

From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 2/2] drm/i915: improve assert_panel_unlocked
Date: Tue, 26 Aug 2014 16:38:43 +0200
Message-ID: <20140826143843.GD15520@phenom.ffwll.local>
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To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Aug 22, 2014 at 11:00:15AM +0300, Ville Syrj=E4l=E4 wrote:
> On Thu, Aug 21, 2014 at 12:01:07PM -0300, Paulo Zanoni wrote:
> > 2014-08-21 11:56 GMT-03:00 Ville Syrj=E4l=E4 <ville.syrjala@linux.intel=
.com>:
> > > On Thu, Aug 21, 2014 at 03:06:26PM +0300, Jani Nikula wrote:
> > >> Fix assert_panel_unlocked for vlv/chv, and improve it a bit for
> > >> non-LVDS. Also don't pretend it works for DDI. There's still work to=
 do
> > >> to get this right for eDP on PCH platforms, but this is a start.
> > >>
> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> > >>
> > >> ---
> > >>
> > >> So I wanted to quickly fix assert_panel_unlocked, but for such a sho=
rt
> > >> piece of code it's too involved to _quickly_ get right across all
> > >> platforms. I think this is a worthwhile improvement though.
> > >> ---
> > >>  drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++++++++-----=
--
> > >>  1 file changed, 20 insertions(+), 7 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/=
i915/intel_display.c
> > >> index fe1d00dc9ef5..d6b48496d7f4 100644
> > >> --- a/drivers/gpu/drm/i915/intel_display.c
> > >> +++ b/drivers/gpu/drm/i915/intel_display.c
> > >> @@ -1193,17 +1193,33 @@ void assert_fdi_rx_pll(struct drm_i915_priva=
te *dev_priv,
> > >>  static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
> > >>                                 enum pipe pipe)
> > >>  {
> > >> -     int pp_reg, lvds_reg;
> > >> +     struct drm_device *dev =3D dev_priv->dev;
> > >> +     int pp_reg;
> > >>       u32 val;
> > >>       enum pipe panel_pipe =3D PIPE_A;
> > >>       bool locked =3D true;
> > >>
> > >> -     if (HAS_PCH_SPLIT(dev_priv->dev)) {
> > >> +     if (HAS_DDI(dev)) {
> > >> +             /* XXX: this neither works nor gets called for DDI */
> > >
> > > Not sure why the XXX here. Seems to me there's nothing to fix here for
> > > DDI. Maybe just make that a WARN_ON(HAS_DDI()) or just remove the che=
ck
> > > entirely.
> > =

> > As far as I remember, the "abcd" stuff is not even used/needed on DDI.
> > But this is just what my memory tells me, it may be wrong. Someone
> > needs to double-check.
> =

> Bspec just says "spare" for those bits.

Iirc it's also not used for edp on older platforms, but only for lvds.
There's definitely a lot of fun in this area ...
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

