From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox
Date: Thu, 21 Aug 2014 19:01:17 +0200 [thread overview]
Message-ID: <201408211901.17360.marex@denx.de> (raw)
In-Reply-To: <CAOMZO5DNcV1M396vwcyez22NSBpmom4xZ0QGw6Fye6VhCLGPUw@mail.gmail.com>
On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
> On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
> > there something completely else broken on MX6SX ?
>
> Thanks for the review, Marek.
>
> Inspecting this further I think the correct fix would be:
>
> arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 2631beb..e9e6f63 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,7 @@
>
> #define ARCH_MXC
>
> -#define CONFIG_SYS_CACHELINE_SIZE 32
> +#define CONFIG_SYS_CACHELINE_SIZE 64
Well yeah, it would ;-)
Best regards,
Marek Vasut
prev parent reply other threads:[~2014-08-21 17:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-21 16:12 [U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox Fabio Estevam
2014-08-21 16:12 ` [U-Boot] [PATCH v3 2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR Fabio Estevam
2014-08-21 16:22 ` Marek Vasut
2014-08-21 16:21 ` [U-Boot] [PATCH v3 1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox Marek Vasut
2014-08-21 16:41 ` Fabio Estevam
2014-08-21 17:01 ` Marek Vasut [this message]
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