diff for duplicates of <20140828035639.GB4972@localhost> diff --git a/a/1.txt b/N1/1.txt index 32d555f..7e8d76b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -68,7 +68,7 @@ You should probably use address-cells/size-cells 2/2 on a 64-bit platform. > + mshc2 = &mmc_2; > + }; > + -> + chipid@10000000 { +> + chipid at 10000000 { > + compatible = "samsung,exynos4210-chipid"; > + reg = <0x10000000 0x100>; > + }; @@ -79,7 +79,7 @@ You should probably use address-cells/size-cells 2/2 on a 64-bit platform. Why size-cells=2? Can you not fit a cpuid in 32 bits? -> + cpu@0 { +> + cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a57", "arm,armv8"; > + reg = <0x0 0x0>; @@ -93,7 +93,7 @@ Why size-cells=2? Can you not fit a cpuid in 32 bits? > + #clock-cells = <0>; > + }; > + -> + gic: interrupt-controller@11001000 { +> + gic: interrupt-controller at 11001000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -104,7 +104,7 @@ Why size-cells=2? Can you not fit a cpuid in 32 bits? > + <0x11006000 0x2000>; > + }; > + -> + hsi2c_0: hsi2c@13640000 { +> + hsi2c_0: hsi2c at 13640000 { > + compatible = "samsung,exynos7-hsi2c"; Is the i2c controller here completely new? @@ -122,7 +122,7 @@ Also, please use 'i2c' for node name on these nodes. > + status = "disabled"; > + }; > + -> + hsi2c_1: hsi2c@13650000 { +> + hsi2c_1: hsi2c at 13650000 { > + compatible = "samsung,exynos7-hsi2c"; > + reg = <0x13650000 0x1000>; > + interrupts = <0 442 0>; @@ -135,19 +135,19 @@ Also, please use 'i2c' for node name on these nodes. > + status = "disabled"; > + }; > + -> + hsi2c_2: hsi2c@14E60000 { +> + hsi2c_2: hsi2c at 14E60000 { I much prefer lowercase hex in unit addresses (and reg entries) below. I know 32-bit uses uppercase, but let's switch going forward here. -> + mct@101C0000 { +> + mct at 101C0000 { > + compatible = "samsung,exynos4210-mct"; Please just do away with MCT here, and use architected timers going forward. There really shouldn't be a need to keep supporting MCT any more -- it's a construct from before arch timers on Cortex-A9. -> + mmc_0: mmc@15740000 { +> + mmc_0: mmc at 15740000 { > + compatible = "samsung,exynos7-dw-mshc-smu"; Is this controller backwards compatible with exynos5 ones? diff --git a/a/content_digest b/N1/content_digest index 5d3ceb6..5990099 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,9 @@ "ref\01409132660-1898-1-git-send-email-ch.naveen@samsung.com\0" "ref\01409132660-1898-3-git-send-email-ch.naveen@samsung.com\0" - "From\0Olof Johansson <olof@lixom.net>\0" - "Subject\0Re: [PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7\0" + "From\0olof@lixom.net (Olof Johansson)\0" + "Subject\0[PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7\0" "Date\0Wed, 27 Aug 2014 20:56:39 -0700\0" - "To\0Naveen Krishna Chatradhi <ch.naveen@samsung.com>\0" - "Cc\0catalin.marinas@arm.com" - naveenkrishna.ch@gmail.com - linux-arm-kernel@lists.infradead.org - linux-samsung-soc@vger.kernel.org - devicetree@vger.kernel.org - cpgs@samsung.com - Thomas Abraham <thomas.ab@samsung.com> - " Rob Herring <robh@kernel.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -84,7 +76,7 @@ "> +\t\tmshc2 = &mmc_2;\n" "> +\t};\n" "> +\n" - "> +\tchipid@10000000 {\n" + "> +\tchipid at 10000000 {\n" "> +\t\tcompatible = \"samsung,exynos4210-chipid\";\n" "> +\t\treg = <0x10000000 0x100>;\n" "> +\t};\n" @@ -95,7 +87,7 @@ "\n" "Why size-cells=2? Can you not fit a cpuid in 32 bits?\n" "\n" - "> +\t\tcpu@0 {\n" + "> +\t\tcpu at 0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x0>;\n" @@ -109,7 +101,7 @@ "> +\t\t#clock-cells = <0>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@11001000 {\n" + "> +\tgic: interrupt-controller at 11001000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -120,7 +112,7 @@ "> +\t\t\t<0x11006000 0x2000>;\n" "> +\t};\n" "> +\n" - "> +\thsi2c_0: hsi2c@13640000 {\n" + "> +\thsi2c_0: hsi2c at 13640000 {\n" "> +\t\tcompatible = \"samsung,exynos7-hsi2c\";\n" "\n" "Is the i2c controller here completely new?\n" @@ -138,7 +130,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\thsi2c_1: hsi2c@13650000 {\n" + "> +\thsi2c_1: hsi2c at 13650000 {\n" "> +\t\tcompatible = \"samsung,exynos7-hsi2c\";\n" "> +\t\treg = <0x13650000 0x1000>;\n" "> +\t\tinterrupts = <0 442 0>;\n" @@ -151,19 +143,19 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\thsi2c_2: hsi2c@14E60000 {\n" + "> +\thsi2c_2: hsi2c at 14E60000 {\n" "\n" "I much prefer lowercase hex in unit addresses (and reg entries) below. I\n" "know 32-bit uses uppercase, but let's switch going forward here.\n" "\n" - "> +\tmct@101C0000 {\n" + "> +\tmct at 101C0000 {\n" "> +\t\tcompatible = \"samsung,exynos4210-mct\";\n" "\n" "Please just do away with MCT here, and use architected timers going\n" "forward. There really shouldn't be a need to keep supporting MCT any\n" "more -- it's a construct from before arch timers on Cortex-A9.\n" "\n" - "> +\tmmc_0: mmc@15740000 {\n" + "> +\tmmc_0: mmc at 15740000 {\n" "> +\t\tcompatible = \"samsung,exynos7-dw-mshc-smu\";\n" "\n" "Is this controller backwards compatible with exynos5 ones?\n" @@ -191,4 +183,4 @@ "\n" -Olof -8a4a39439d454d9218f6ba6f6b1c83d3f75a397561b3c2ce9950445f93691a89 +81c3c300e30e6bbae3ed0d3c72063d45a4ca52e919b09a9ff3616ae36cfe9eb7
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