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From: Damien Lespiau <damien.lespiau@intel.com>
To: "Siluvery, Arun" <arun.siluvery@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915: Rework workaround data exporting to debugfs
Date: Mon, 1 Sep 2014 16:04:37 +0100	[thread overview]
Message-ID: <20140901150437.GF1118@strange.amr.corp.intel.com> (raw)
In-Reply-To: <54048689.5090203@linux.intel.com>

On Mon, Sep 01, 2014 at 03:45:29PM +0100, Siluvery, Arun wrote:
> >>+		/*
> >>+		 * Most of workarounds are  masked registers;
> >>+		 * to set a bit in lower 16-bits we set a mask bit in
> >>+		 * upper 16-bits so we can take either of them as mask but
> >>+		 * it doesn't work if the w/a is about clearing a bit so
> >>+		 * use upper 16-bits to cover both cases.
> >>+		 */
> >>+		mask = ro_data.init_context[i+1] >> 16;
> >
> >"Most" doesn't seem good here. Either it's "all" and we're happy, or we
> >need a generic way to describe the W/A (masked register or not). value +
> >mask is generic enough to code for both cases.
> >
> It seems some of them could be unmasked registers.
> We can use 'mask' itself to determine whether it is a
> masked/unmasked register. mask == 0 if it is an unmasked register.

I don't think we can use mask == 0 when it's an unmasked register. In
this case, we still need to be able to have a mask that tells us which
are the interesting bits in the value. If we want something generic that
can be applied to masked and unmasked register, we'll something like:

struct reg_wa {
	unsigned int masked_register : 1;
	u32 addr;
	u32 mask;
	u32 value;
};

So:

1. masked register case:

  - masked_register = 1
  - addr
  - mask (selects the lower 16 bits that are coding for the W/A value)
  - value (it only makes sense to some of the lower 16 bits set here)

2. 'normal' register case

  - masked_register = 0
  - addr
  - mask
  - value

>From that generic description you can cover all cases, eg.

1. the write for masked registers becomes: mask << 16 | value
2. the write for normal registers becomes: (read(addr) & ~mask) | value
2. check a W/A has been applied (both normal and masked register):
	read(addr) & mask == value

We seem to have only masked registers atm, so it's fine to handle just
that case, but if you envision that we'll need more than masked
registers, we need a better W/A definition.
  
-- 
Damien

  reply	other threads:[~2014-09-01 15:04 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-01 13:28 [PATCH 0/4] Rework workaround init fn for BDW and CHV Arun Siluvery
2014-09-01 13:28 ` [PATCH 1/4] drm/i915: Rework workaround init functions " Arun Siluvery
2014-09-02  9:14   ` [PATCH v2] " Arun Siluvery
2014-09-02  9:45     ` Damien Lespiau
2014-09-02  9:49       ` Damien Lespiau
2014-09-02  9:51       ` Chris Wilson
2014-09-01 13:28 ` [PATCH 2/4] drm/i915: Rename intel_wa_registers with a i915_ prefix Arun Siluvery
2014-09-01 13:28 ` [PATCH 3/4] drm/i915: Don't restrict i915_wa_registers to BDW Arun Siluvery
2014-09-01 13:28 ` [PATCH 4/4] drm/i915: Rework workaround data exporting to debugfs Arun Siluvery
2014-09-01 14:06   ` Damien Lespiau
2014-09-01 14:45     ` Siluvery, Arun
2014-09-01 15:04       ` Damien Lespiau [this message]
2014-09-02  9:15   ` [PATCH v2] " Arun Siluvery
2014-09-02  9:56     ` Daniel Vetter

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