Re: [PATCH 2/2] i2c-mxs: fixed PIO NACK error instead of timeout

[Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>]

On Tuesday, September 09, 2014 at 11:27:36 AM, Janusz Użycki wrote:
> W dniu 2014-09-08 20:33, Marek Vasut pisze:
> > On Monday, September 08, 2014 at 08:06:12 PM, Janusz Użycki wrote:
> >> Subject: [PATCH 2/2] i2c-mxs: fixed PIO NACK error instead of timeout
> >> 
> >>    (1000ms)
> >> 
> >> i2cdetect scanned i2c bus very slow if address was not occupied by any
> >> device.
> > 
> > Shouldn't this check be used only after the 'SELECT' command ?
> 
> It looks |||mxs_i2c_isr()| for DMA transfer does not differentiate
> commands also
> and does not mask irqs for each command.
> 
> |STAT_GOT_A_NAK|  is a separate bit.|CTRL1_NO_SLAVE_ACK_IRQ can be set
> 
> both after SELECT and WRITE command. Should we differentiate?

What about writes that take long time, will checking this bit not break them ? 
(like programming a slow eeprom or such)

> |Checking CTRL1_NO_SLAVE_ACK_IRQ |bit for SELECT command will increase
> 
> code size only
> without special profit. Current PIO implementation also gathers all errors
> together and reads them on the end by mxs_i2c_pio_check_error_state().
> Probably mxs_i2c_pio_check_error_state() call or
> enabling interrupt masks for PIO could be better than
> direct |CTRL1_NO_SLAVE_ACK_IRQ |bit checking for clear code.
> It also could support multimaster for PIO (MASTER_LOSS).

Actually, the PIO is explicitly IRQ-less and is used only for transferring very 
short amounts of data.

Best regards,
Marek Vasut