From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: Andi Kleen <andi@firstfloor.org>,
LKML <linux-kernel@vger.kernel.org>,
Ingo Molnar <mingo@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 2/2] perf, x86: Use INTEL_FLAGS_UEVENT_CONSTRAINT for PRECDIST
Date: Wed, 10 Sep 2014 10:39:49 +0200 [thread overview]
Message-ID: <20140910083949.GR6758@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <CABPqkBQBVRph9+aXC6F3=QxkVXXYVH8wM4rPwKBY8dpCtf1z_A@mail.gmail.com>
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On Wed, Sep 10, 2014 at 10:37:14AM +0200, Stephane Eranian wrote:
> On Wed, Sep 10, 2014 at 9:59 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> > On Wed, Sep 10, 2014 at 09:59:26AM +0200, Peter Zijlstra wrote:
> >> On Tue, Sep 09, 2014 at 05:49:08PM -0700, Andi Kleen wrote:
> >> > From: Andi Kleen <ak@linux.intel.com>
> >> >
> >> > The earlier commit 86a04461a made near all PEBS on
> >> > Sandy/IvyBridge/Haswell to reject non zero flags.
> >>
> >> What's magic about nehalem and westmere?
> >
> > And core2 and whatever else we support PEBS for, for that matter.
>
> nhm, wsm, core2 do not have precise distribution (PREC_DIST) umask to
> inst_Retired.
That was a comment to 86a04461a, I should have spotted it at the time.
There is no sane reason to only change PEBS for a subset of chips.
That needs to be fixed before I'll take anything else from Andi.
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next prev parent reply other threads:[~2014-09-10 8:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-10 0:49 [PATCH 1/2] perf, x86: Add INTEL_FLAGS_UEVENT_CONSTRAINT Andi Kleen
2014-09-10 0:49 ` [PATCH 2/2] perf, x86: Use INTEL_FLAGS_UEVENT_CONSTRAINT for PRECDIST Andi Kleen
2014-09-10 7:59 ` Peter Zijlstra
2014-09-10 7:59 ` Peter Zijlstra
2014-09-10 8:37 ` Stephane Eranian
2014-09-10 8:39 ` Peter Zijlstra [this message]
2014-09-10 14:02 ` Andi Kleen
2014-09-10 14:22 ` Peter Zijlstra
2014-09-23 9:58 ` Peter Zijlstra
2014-10-03 4:02 ` Ingo Molnar
2014-09-10 20:38 ` Thomas Gleixner
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