From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: HSW always use GGTT selector for secure batches Date: Wed, 10 Sep 2014 15:00:03 +0300 Message-ID: <20140910120003.GR4193@intel.com> References: <20140910103045.GQ4193@intel.com> <1410347907-1020-1-git-send-email-chris@chris-wilson.co.uk> <20140910112143.GB31074@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id E79386E439 for ; Wed, 10 Sep 2014 05:00:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20140910112143.GB31074@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Sep 10, 2014 at 12:21:43PM +0100, Chris Wilson wrote: > On Wed, Sep 10, 2014 at 12:18:27PM +0100, Chris Wilson wrote: > > gen6 and earlier conflate address space selection (ppgtt vs ggtt) with > > the security bit (i.e. only privileged batches were allowed to run from > > ggtt). From Haswell onwards, you are able to select the security bit > = > ggtt). For Haswell only, you are able to select the security bit > = > > separate from the address space - and we always requested to use ppgtt. > > This breaks the golden render state batch execution with full-ppgtt as > > that is only present in the global GTT and more generally any secure > > batch that is not colocated in the ppgtt and ggtt. So we need to > > disable the use of the ppgtt selector bit for secure batches, or else we > > hang immediately upon boot and thence after every GPU reset... > > = > > v2: Only HSW differentiates between secure dispatch and ggtt, so simply > > ignore the differentiation and always use secure=3D=3Dggtt. > > = > > Signed-off-by: Chris Wilson > > Cc: Ville Syrj=E4l=E4 Reviewed-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/= i915/intel_ringbuffer.c > > index 109de2eeb9a8..25795f2efdcb 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -2203,8 +2203,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_= cs *ring, > > return ret; > > = > > intel_ring_emit(ring, > > - MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW | > > - (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW)); > > + MI_BATCH_BUFFER_START | > > + (flags & I915_DISPATCH_SECURE ? > > + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); > > /* bit0-7 is the length on GEN6+ */ > > intel_ring_emit(ring, offset); > > intel_ring_advance(ring); > > -- = > > 2.1.0 > > = > = > -- = > Chris Wilson, Intel Open Source Technology Centre -- = Ville Syrj=E4l=E4 Intel OTC