From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Thu, 11 Sep 2014 17:47:10 +0100 Subject: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer In-Reply-To: <1410452204-7277-1-git-send-email-dianders@chromium.org> References: <1410452204-7277-1-git-send-email-dianders@chromium.org> Message-ID: <20140911164710.GW6158@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > On systems like the above, it doesn't make sense to use the virtual > counter. There's nobody managing the offset and each time a core goes > down and comes back up it will get reinitialized to some other random > value. You probably need to rephrase this slightly, as there *is* still a requirement on the hypervisor/firmware (actually, two!). See below. > Let's add a property to the device tree to say that we shouldn't use > the virtual timer. Firmware could potentially remove this property > before passing the device tree to the kernel if it really wants the > kernel to use a virtual timer. > > Note that it's been said that ARM64 (ARMv8) systems the firmware and > kernel really can't be architected as described above. That means > using the physical timer like this really only makes sense for ARMv7 > systems. I'd go further: this only makes sense if you're booting in secure SVC mode. > In order for this patch to do anything useful, we also need Sonny's > patch at > > Signed-off-by: Doug Anderson > Signed-off-by: Sonny Rao > --- > Changes in v2: > - Add "#ifdef CONFIG_ARM" as per Will Deacon > > Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ > drivers/clocksource/arm_arch_timer.c | 5 +++++ > 2 files changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt > index 37b2caf..876d32b 100644 > --- a/Documentation/devicetree/bindings/arm/arch_timer.txt > +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt > @@ -22,6 +22,12 @@ to deliver its interrupts via SPIs. > - always-on : a boolean property. If present, the timer is powered through an > always-on power domain, therefore it never loses context. > > +** Optional properties: > + > +- arm,use-physical-timer : Don't ever use the virtual timer, just use the > + physical one. Not supported for ARM64. I'd say `Only supported for ARM' to better match what we've done. Probably also worth mentioning that this relies on the hypervisor/firmware having set CNTHCTL.PL1PCEN and CNTHCTL.EL1PCTEN (but assumedly made a mess of CNTVOFF ;) if you want to boot on the non-secure side (e.g. as a guest). Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer Date: Thu, 11 Sep 2014 17:47:10 +0100 Message-ID: <20140911164710.GW6158@arm.com> References: <1410452204-7277-1-git-send-email-dianders@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1410452204-7277-1-git-send-email-dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Doug Anderson Cc: "olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org" , Sonny Rao , Catalin Marinas , Mark Rutland , Stephen Boyd , Marc Zyngier , Sudeep Holla , Christopher Covington , Lorenzo Pieralisi , Thomas Gleixner , Daniel Lezcano , Nathan Lynch , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , Pawel Moll , "ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org" , "galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > On systems like the above, it doesn't make sense to use the virtual > counter. There's nobody managing the offset and each time a core goes > down and comes back up it will get reinitialized to some other random > value. You probably need to rephrase this slightly, as there *is* still a requirement on the hypervisor/firmware (actually, two!). See below. > Let's add a property to the device tree to say that we shouldn't use > the virtual timer. Firmware could potentially remove this property > before passing the device tree to the kernel if it really wants the > kernel to use a virtual timer. > > Note that it's been said that ARM64 (ARMv8) systems the firmware and > kernel really can't be architected as described above. That means > using the physical timer like this really only makes sense for ARMv7 > systems. I'd go further: this only makes sense if you're booting in secure SVC mode. > In order for this patch to do anything useful, we also need Sonny's > patch at > > Signed-off-by: Doug Anderson > Signed-off-by: Sonny Rao > --- > Changes in v2: > - Add "#ifdef CONFIG_ARM" as per Will Deacon > > Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ > drivers/clocksource/arm_arch_timer.c | 5 +++++ > 2 files changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt > index 37b2caf..876d32b 100644 > --- a/Documentation/devicetree/bindings/arm/arch_timer.txt > +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt > @@ -22,6 +22,12 @@ to deliver its interrupts via SPIs. > - always-on : a boolean property. If present, the timer is powered through an > always-on power domain, therefore it never loses context. > > +** Optional properties: > + > +- arm,use-physical-timer : Don't ever use the virtual timer, just use the > + physical one. Not supported for ARM64. I'd say `Only supported for ARM' to better match what we've done. Probably also worth mentioning that this relies on the hypervisor/firmware having set CNTHCTL.PL1PCEN and CNTHCTL.EL1PCTEN (but assumedly made a mess of CNTVOFF ;) if you want to boot on the non-secure side (e.g. as a guest). Will -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757200AbaIKQrN (ORCPT ); Thu, 11 Sep 2014 12:47:13 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:55775 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756164AbaIKQrL (ORCPT ); Thu, 11 Sep 2014 12:47:11 -0400 Date: Thu, 11 Sep 2014 17:47:10 +0100 From: Will Deacon To: Doug Anderson Cc: "olof@lixom.net" , Sonny Rao , Catalin Marinas , Mark Rutland , Stephen Boyd , Marc Zyngier , Sudeep Holla , Christopher Covington , Lorenzo Pieralisi , Thomas Gleixner , Daniel Lezcano , Nathan Lynch , "linux-arm-kernel@lists.infradead.org" , "robh+dt@kernel.org" , Pawel Moll , "ijc+devicetree@hellion.org.uk" , "galak@codeaurora.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2] clocksource: arch_timer: Allow the device tree to specify the physical timer Message-ID: <20140911164710.GW6158@arm.com> References: <1410452204-7277-1-git-send-email-dianders@chromium.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1410452204-7277-1-git-send-email-dianders@chromium.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 11, 2014 at 05:16:44PM +0100, Doug Anderson wrote: > Some 32-bit (ARMv7) systems are architected like this: > > * The firmware doesn't know and doesn't care about hypervisor mode and > we don't want to add the complexity of hypervisor there. > > * The firmware isn't involved in SMP bringup or resume. > > * The ARCH timer come up with an uninitialized offset between the > virtual and physical counters. Each core gets a different random > offset. > > On systems like the above, it doesn't make sense to use the virtual > counter. There's nobody managing the offset and each time a core goes > down and comes back up it will get reinitialized to some other random > value. You probably need to rephrase this slightly, as there *is* still a requirement on the hypervisor/firmware (actually, two!). See below. > Let's add a property to the device tree to say that we shouldn't use > the virtual timer. Firmware could potentially remove this property > before passing the device tree to the kernel if it really wants the > kernel to use a virtual timer. > > Note that it's been said that ARM64 (ARMv8) systems the firmware and > kernel really can't be architected as described above. That means > using the physical timer like this really only makes sense for ARMv7 > systems. I'd go further: this only makes sense if you're booting in secure SVC mode. > In order for this patch to do anything useful, we also need Sonny's > patch at > > Signed-off-by: Doug Anderson > Signed-off-by: Sonny Rao > --- > Changes in v2: > - Add "#ifdef CONFIG_ARM" as per Will Deacon > > Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ > drivers/clocksource/arm_arch_timer.c | 5 +++++ > 2 files changed, 11 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt > index 37b2caf..876d32b 100644 > --- a/Documentation/devicetree/bindings/arm/arch_timer.txt > +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt > @@ -22,6 +22,12 @@ to deliver its interrupts via SPIs. > - always-on : a boolean property. If present, the timer is powered through an > always-on power domain, therefore it never loses context. > > +** Optional properties: > + > +- arm,use-physical-timer : Don't ever use the virtual timer, just use the > + physical one. Not supported for ARM64. I'd say `Only supported for ARM' to better match what we've done. Probably also worth mentioning that this relies on the hypervisor/firmware having set CNTHCTL.PL1PCEN and CNTHCTL.EL1PCTEN (but assumedly made a mess of CNTVOFF ;) if you want to boot on the non-secure side (e.g. as a guest). Will