From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v2 1/2] gpio: Increase ARCH_NR_GPIOs to 512 Date: Mon, 15 Sep 2014 18:50:34 +0200 Message-ID: <201409151850.34472.arnd@arndb.de> References: <1410790185-31101-1-git-send-email-mika.westerberg@linux.intel.com> Mime-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Return-path: Received: from mout.kundenserver.de ([212.227.17.10]:51025 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754046AbaIOQuw (ORCPT ); Mon, 15 Sep 2014 12:50:52 -0400 In-Reply-To: <1410790185-31101-1-git-send-email-mika.westerberg@linux.intel.com> Sender: linux-gpio-owner@vger.kernel.org List-Id: linux-gpio@vger.kernel.org To: Mika Westerberg Cc: Linus Walleij , Alexandre Courbot , Alan Cox , Ning Li , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org On Monday 15 September 2014, Mika Westerberg wrote: > Some newer Intel SoCs, like Braswell already have more than 256 GPIOs > available so the default limit is exceeded. Instead of adding more > architecture specific gpio.h files with custom ARCH_NR_GPIOs we increase > the gpiolib default limit to be twice the current. > > Signed-off-by: Mika Westerberg > --- > Changes to previous version is that now we increase the common limit > instead of adding x86 specific gpio.h Can you please include the reasoning for this decision in the changeset description? I'm sure you have your reasons, but from the text above, it sounds like a rather bad idea. What other architectures are impacted by this, and what is the kernel size cost for it on those architectures? Arnd