From: Bjorn Helgaas <bhelgaas@google.com>
To: Pratyush Anand <pratyush.anand@st.com>
Cc: mohit.kumar@st.com, linux-pci@vger.kernel.org
Subject: Re: [PATCH V2] PCIe: SPEAr13XX: Pass config resource through reg property
Date: Mon, 22 Sep 2014 14:21:26 -0600 [thread overview]
Message-ID: <20140922202126.GD1880@google.com> (raw)
In-Reply-To: <c5feb916f14d19e4c636a5af89be48df5097b500.1409720201.git.pratyush.anand@st.com>
On Wed, Sep 03, 2014 at 10:50:49AM +0530, Pratyush Anand wrote:
> PCIe configuration space should be passed through reg property, rather
> than through ranges property. This patch does the correction for
> SPEAr13XX SOCs.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Applied with Mohit's ack to pci/host-spear for v3.18, thanks!
> ---
> arch/arm/boot/dts/spear1310.dtsi | 18 +++++++++---------
> arch/arm/boot/dts/spear1340.dtsi | 6 +++---
> drivers/pci/host/pcie-spear13xx.c | 2 +-
> 3 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
> index fa5f2bb5f106..9d342920695a 100644
> --- a/arch/arm/boot/dts/spear1310.dtsi
> +++ b/arch/arm/boot/dts/spear1310.dtsi
> @@ -85,7 +85,8 @@
>
> pcie0: pcie@b1000000 {
> compatible = "st,spear1340-pcie", "snps,dw-pcie";
> - reg = <0xb1000000 0x4000>;
> + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
> + reg-names = "dbi", "config";
> interrupts = <0 68 0x4>;
> interrupt-map-mask = <0 0 0 0>;
> interrupt-map = <0x0 0 &gic 0 68 0x4>;
> @@ -95,15 +96,15 @@
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> - 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> status = "disabled";
> };
>
> pcie1: pcie@b1800000 {
> compatible = "st,spear1340-pcie", "snps,dw-pcie";
> - reg = <0xb1800000 0x4000>;
> + reg = <0xb1800000 0x4000>, <0x90000000 0x20000>;
> + reg-names = "dbi", "config";
> interrupts = <0 69 0x4>;
> interrupt-map-mask = <0 0 0 0>;
> interrupt-map = <0x0 0 &gic 0 69 0x4>;
> @@ -113,15 +114,15 @@
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */
> - 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
> 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
> status = "disabled";
> };
>
> pcie2: pcie@b4000000 {
> compatible = "st,spear1340-pcie", "snps,dw-pcie";
> - reg = <0xb4000000 0x4000>;
> + reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>;
> + reg-names = "dbi", "config";
> interrupts = <0 70 0x4>;
> interrupt-map-mask = <0 0 0 0>;
> interrupt-map = <0x0 0 &gic 0 70 0x4>;
> @@ -131,8 +132,7 @@
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */
> - 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
> 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> status = "disabled";
> };
> diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
> index e71df0f2cb52..13e1aa33daa2 100644
> --- a/arch/arm/boot/dts/spear1340.dtsi
> +++ b/arch/arm/boot/dts/spear1340.dtsi
> @@ -50,7 +50,8 @@
>
> pcie0: pcie@b1000000 {
> compatible = "st,spear1340-pcie", "snps,dw-pcie";
> - reg = <0xb1000000 0x4000>;
> + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
> + reg-names = "dbi", "config";
> interrupts = <0 68 0x4>;
> interrupt-map-mask = <0 0 0 0>;
> interrupt-map = <0x0 0 &gic 0 68 0x4>;
> @@ -60,8 +61,7 @@
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> - ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
> - 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
> 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
> status = "disabled";
> };
> diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
> index 6dea9e43a75c..85f594e1708f 100644
> --- a/drivers/pci/host/pcie-spear13xx.c
> +++ b/drivers/pci/host/pcie-spear13xx.c
> @@ -340,7 +340,7 @@ static int __init spear13xx_pcie_probe(struct platform_device *pdev)
>
> pp->dev = dev;
>
> - dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
> if (IS_ERR(pp->dbi_base)) {
> dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
> --
> 1.8.1.2
>
> --
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prev parent reply other threads:[~2014-09-22 20:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-03 5:20 [PATCH V2] PCIe: SPEAr13XX: Pass config resource through reg property Pratyush Anand
2014-09-03 6:19 ` Mohit KUMAR DCG
2014-09-22 20:21 ` Bjorn Helgaas [this message]
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