From: Bjorn Helgaas <bhelgaas@google.com>
To: "Chen, Gong" <gong.chen@linux.intel.com>
Cc: rdunlap@infradead.org, bp@alien8.de, tony.luck@intel.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Heather Brown <hbrown@hp.com>
Subject: Re: [RESEND 0/5] PCIe, AER: Misc cleanup
Date: Thu, 25 Sep 2014 09:54:02 -0600 [thread overview]
Message-ID: <20140925155402.GB12200@google.com> (raw)
In-Reply-To: <1407910961-7798-1-git-send-email-gong.chen@linux.intel.com>
[+cc Heather]
On Wed, Aug 13, 2014 at 02:22:36AM -0400, Chen, Gong wrote:
>
> No response since last commit so spread it to a bigger range.
>
> This patch series is for AER related cleanup & update based on PCIe
> SPEC r3.0.
I applied patches 1, 2 (modified as described in my response to it), 3, and
4 to pci/aer for v3.19, thanks!
I didn't apply patch 5 because it apparently doesn't fix a reported bug,
and it has the potential to break hardware that used the PCIe r1.0
definition of the "Training Error" bit.
Bjorn
prev parent reply other threads:[~2014-09-25 15:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-13 6:22 [RESEND 0/5] PCIe, AER: Misc cleanup Chen, Gong
2014-08-13 6:22 ` [RESEND 1/5] RAS, trace: Update error definition format Chen, Gong
2014-08-13 6:22 ` [RESEND 2/5] PCIe, AER: Replenish missed AER status bits for AER driver Chen, Gong
2014-09-05 23:15 ` Bjorn Helgaas
2014-09-09 7:03 ` Chen, Gong
2014-09-25 15:51 ` Bjorn Helgaas
2014-08-13 6:22 ` [RESEND 3/5] PCIe, trace: Replenish missed AER status bits for PCIE trace I/F Chen, Gong
2014-08-13 6:22 ` [RESEND 4/5] PCIe, AER: Make AER UC status naming clearer Chen, Gong
2014-08-13 6:22 ` [RESEND RFC 5/5] PCIe, AER: Update initial value of UC error mask Chen, Gong
2014-09-05 23:34 ` Bjorn Helgaas
2014-09-09 7:12 ` Chen, Gong
2014-08-13 13:52 ` [RESEND 0/5] PCIe, AER: Misc cleanup Bjorn Helgaas
2014-08-14 1:52 ` Chen, Gong
2014-09-02 1:31 ` Chen, Gong
2014-09-25 15:54 ` Bjorn Helgaas [this message]
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