diff for duplicates of <20140925213959.19023.80648@quantum> diff --git a/a/1.txt b/N1/1.txt index f0c78b5..d90e61b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,70 +2,59 @@ Quoting Jingchang Lu (2014-09-22 23:46:46) > The IP is shared by PPC and ARM, this renames it to qoriq for better > represention, and this also adds the CLK_OF_DECLARE support for being > initialized by of_clk_init() on ARM. -> = - +> > Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> > --- > changes in v4: > remove "corenet" literals omitted in v3 remove. -> = - +> > changes in v3: > generate the patch with -M -C option -> = - +> > changes in v2: > rename the driver name to ppc-qoriq.c for shared on PPC and ARM. -> = - +> > drivers/clk/Kconfig | 9 +++++---- > drivers/clk/Makefile | 2 +- -> drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} | 27 +++++++++++++++---= --------- +> drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 27 +++++++++++++++----------- > 3 files changed, 22 insertions(+), 16 deletions(-) -> rename drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} (89%) -> = - +> rename drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (89%) +> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > index 85131ae..f5f76cb 100644 > --- a/drivers/clk/Kconfig > +++ b/drivers/clk/Kconfig > @@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN -> Support for the Analog Devices axi-clkgen pcore clock generator= - for Xilinx +> Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx > FPGAs. It is commonly used in Analog Devices' reference designs. -> = - +> > -config CLK_PPC_CORENET > - bool "Clock driver for PowerPC corenet platforms" > - depends on PPC_E500MC && OF > +config CLK_QORIQ -> + bool "Clock driver for PowerPC corenet and compatible ARM-based p= -latforms" +> + bool "Clock driver for PowerPC corenet and compatible ARM-based platforms" > + depends on (PPC_E500MC || ARM) && OF > ---help--- > This adds the clock driver support for Freescale PowerPC corenet > - platforms using common clock framework. -> + platforms and compatible Freescale ARM based platforms using co= -mmon +> + platforms and compatible Freescale ARM based platforms using common > + clock framework. -> = - +> > config COMMON_CLK_XGENE > bool "Clock driver for APM XGene SoC" > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > index 27c542b..20f42e9 100644 > --- a/drivers/clk/Makefile > +++ b/drivers/clk/Makefile -> @@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) +=3D clk-moxart.o -> obj-$(CONFIG_ARCH_NOMADIK) +=3D clk-nomadik.o -> obj-$(CONFIG_ARCH_NSPIRE) +=3D clk-nspire.o -> obj-$(CONFIG_COMMON_CLK_PALMAS) +=3D clk-palmas.o -> -obj-$(CONFIG_CLK_PPC_CORENET) +=3D clk-ppc-corenet.o -> +obj-$(CONFIG_CLK_QORIQ) +=3D clk-qoriq.o -> obj-$(CONFIG_COMMON_CLK_S2MPS11) +=3D clk-s2mps11.o -> obj-$(CONFIG_COMMON_CLK_SI5351) +=3D clk-si5351.o -> obj-$(CONFIG_COMMON_CLK_SI570) +=3D clk-si570.o +> @@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o +> obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o +> obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o +> obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o +> -obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o +> +obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o +> obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o +> obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o +> obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o > diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c > similarity index 89% > rename from drivers/clk/clk-ppc-corenet.c @@ -73,68 +62,56 @@ mmon > index 8e58edf..cba8abe 100644 > --- a/drivers/clk/clk-ppc-corenet.c > +++ b/drivers/clk/clk-qoriq.c -> @@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *= -np) -> = - -> base =3D of_iomap(np, 0); +> @@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *np) +> +> base = of_iomap(np, 0); > if (!base) { > - pr_err("clk-ppc: iomap error\n"); > + pr_err("clk-qoriq: iomap error\n"); > return; > } -> = - -> @@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *no= -de) +> +> @@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *node) > u32 rate; -> = - +> > if (!np) { > - pr_err("ppc-clk: could not get parent node\n"); > + pr_err("qoriq-clk: could not get parent node\n"); > return; > } -> = - -> @@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __init= -const =3D { +> +> @@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __initconst = { > {} > }; -> = - +> > -static int __init ppc_corenet_clk_probe(struct platform_device *pdev) > +static int __init qoriq_clk_probe(struct platform_device *pdev) > { > of_clk_init(clk_match); -> = - +> > return 0; > } -> = - -> -static const struct of_device_id ppc_clk_ids[] __initconst =3D { -> +static const struct of_device_id qoriq_clk_ids[] __initconst =3D { -> { .compatible =3D "fsl,qoriq-clockgen-1.0", }, -> { .compatible =3D "fsl,qoriq-clockgen-2.0", }, +> +> -static const struct of_device_id ppc_clk_ids[] __initconst = { +> +static const struct of_device_id qoriq_clk_ids[] __initconst = { +> { .compatible = "fsl,qoriq-clockgen-1.0", }, +> { .compatible = "fsl,qoriq-clockgen-2.0", }, > {} > }; -> = - -> -static struct platform_driver ppc_corenet_clk_driver __initdata =3D { -> +static struct platform_driver qoriq_clk_driver __initdata =3D { -> .driver =3D { -> - .name =3D "ppc_corenet_clock", -> + .name =3D "qoriq_clock", -> .owner =3D THIS_MODULE, -> - .of_match_table =3D ppc_clk_ids, -> + .of_match_table =3D qoriq_clk_ids, +> +> -static struct platform_driver ppc_corenet_clk_driver __initdata = { +> +static struct platform_driver qoriq_clk_driver __initdata = { +> .driver = { +> - .name = "ppc_corenet_clock", +> + .name = "qoriq_clock", +> .owner = THIS_MODULE, +> - .of_match_table = ppc_clk_ids, +> + .of_match_table = qoriq_clk_ids, > }, -> - .probe =3D ppc_corenet_clk_probe, -> + .probe =3D qoriq_clk_probe, +> - .probe = ppc_corenet_clk_probe, +> + .probe = qoriq_clk_probe, > }; -> = - +> > -static int __init ppc_corenet_clk_init(void) > +static int __init qoriq_clk_init(void) > { @@ -144,21 +121,16 @@ const =3D { > -subsys_initcall(ppc_corenet_clk_init); > +subsys_initcall(qoriq_clk_init); > + -> +CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0", core_pll_ini= -t); -> +CLK_OF_DECLARE(qoriq_core_pll_v2, "fsl,qoriq-core-pll-2.0", core_pll_ini= -t); -> +CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0", core_mux_ini= -t); -> +CLK_OF_DECLARE(qoriq_core_mux_v2, "fsl,qoriq-core-mux-2.0", core_mux_ini= -t); +> +CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0", core_pll_init); +> +CLK_OF_DECLARE(qoriq_core_pll_v2, "fsl,qoriq-core-pll-2.0", core_pll_init); +> +CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0", core_mux_init); +> +CLK_OF_DECLARE(qoriq_core_mux_v2, "fsl,qoriq-core-mux-2.0", core_mux_init); Is there binding documentation for these compatibles? Regards, Mike -> -- = - +> -- > 1.8.0 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index c402592..1887cf8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,84 +1,67 @@ "ref\01411454806-8214-1-git-send-email-jingchang.lu@freescale.com\0" - "From\0Mike Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support\0" + "From\0mturquette@linaro.org (Mike Turquette)\0" + "Subject\0[PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support\0" "Date\0Thu, 25 Sep 2014 14:39:59 -0700\0" - "To\0Jingchang Lu <jingchang.lu@freescale.com>" - "\0" - "Cc\0scottwood@freescale.com" - linuxppc-dev@lists.ozlabs.org - linux-kernel@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " Jingchang Lu <jingchang.lu@freescale.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Jingchang Lu (2014-09-22 23:46:46)\n" "> The IP is shared by PPC and ARM, this renames it to qoriq for better\n" "> represention, and this also adds the CLK_OF_DECLARE support for being\n" "> initialized by of_clk_init() on ARM.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>\n" "> ---\n" "> changes in v4:\n" "> remove \"corenet\" literals omitted in v3 remove.\n" - "> =\n" - "\n" + "> \n" "> changes in v3:\n" "> generate the patch with -M -C option\n" - "> =\n" - "\n" + "> \n" "> changes in v2:\n" "> rename the driver name to ppc-qoriq.c for shared on PPC and ARM.\n" - "> =\n" - "\n" + "> \n" "> drivers/clk/Kconfig | 9 +++++----\n" "> drivers/clk/Makefile | 2 +-\n" - "> drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} | 27 +++++++++++++++---=\n" - "--------\n" + "> drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 27 +++++++++++++++-----------\n" "> 3 files changed, 22 insertions(+), 16 deletions(-)\n" - "> rename drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} (89%)\n" - "> =\n" - "\n" + "> rename drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (89%)\n" + "> \n" "> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\n" "> index 85131ae..f5f76cb 100644\n" "> --- a/drivers/clk/Kconfig\n" "> +++ b/drivers/clk/Kconfig\n" "> @@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN\n" - "> Support for the Analog Devices axi-clkgen pcore clock generator=\n" - " for Xilinx\n" + "> Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx\n" "> FPGAs. It is commonly used in Analog Devices' reference designs.\n" - "> =\n" - "\n" + "> \n" "> -config CLK_PPC_CORENET\n" "> - bool \"Clock driver for PowerPC corenet platforms\"\n" "> - depends on PPC_E500MC && OF\n" "> +config CLK_QORIQ\n" - "> + bool \"Clock driver for PowerPC corenet and compatible ARM-based p=\n" - "latforms\"\n" + "> + bool \"Clock driver for PowerPC corenet and compatible ARM-based platforms\"\n" "> + depends on (PPC_E500MC || ARM) && OF\n" "> ---help---\n" "> This adds the clock driver support for Freescale PowerPC corenet\n" "> - platforms using common clock framework.\n" - "> + platforms and compatible Freescale ARM based platforms using co=\n" - "mmon\n" + "> + platforms and compatible Freescale ARM based platforms using common\n" "> + clock framework.\n" - "> =\n" - "\n" + "> \n" "> config COMMON_CLK_XGENE\n" "> bool \"Clock driver for APM XGene SoC\"\n" "> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n" "> index 27c542b..20f42e9 100644\n" "> --- a/drivers/clk/Makefile\n" "> +++ b/drivers/clk/Makefile\n" - "> @@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) +=3D clk-moxart.o\n" - "> obj-$(CONFIG_ARCH_NOMADIK) +=3D clk-nomadik.o\n" - "> obj-$(CONFIG_ARCH_NSPIRE) +=3D clk-nspire.o\n" - "> obj-$(CONFIG_COMMON_CLK_PALMAS) +=3D clk-palmas.o\n" - "> -obj-$(CONFIG_CLK_PPC_CORENET) +=3D clk-ppc-corenet.o\n" - "> +obj-$(CONFIG_CLK_QORIQ) +=3D clk-qoriq.o\n" - "> obj-$(CONFIG_COMMON_CLK_S2MPS11) +=3D clk-s2mps11.o\n" - "> obj-$(CONFIG_COMMON_CLK_SI5351) +=3D clk-si5351.o\n" - "> obj-$(CONFIG_COMMON_CLK_SI570) +=3D clk-si570.o\n" + "> @@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o\n" + "> obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o\n" + "> obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o\n" + "> obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o\n" + "> -obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o\n" + "> +obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o\n" + "> obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o\n" + "> obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o\n" + "> obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o\n" "> diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c\n" "> similarity index 89%\n" "> rename from drivers/clk/clk-ppc-corenet.c\n" @@ -86,68 +69,56 @@ "> index 8e58edf..cba8abe 100644\n" "> --- a/drivers/clk/clk-ppc-corenet.c\n" "> +++ b/drivers/clk/clk-qoriq.c\n" - "> @@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *=\n" - "np)\n" - "> =\n" - "\n" - "> base =3D of_iomap(np, 0);\n" + "> @@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node *np)\n" + "> \n" + "> base = of_iomap(np, 0);\n" "> if (!base) {\n" "> - pr_err(\"clk-ppc: iomap error\\n\");\n" "> + pr_err(\"clk-qoriq: iomap error\\n\");\n" "> return;\n" "> }\n" - "> =\n" - "\n" - "> @@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *no=\n" - "de)\n" + "> \n" + "> @@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node *node)\n" "> u32 rate;\n" - "> =\n" - "\n" + "> \n" "> if (!np) {\n" "> - pr_err(\"ppc-clk: could not get parent node\\n\");\n" "> + pr_err(\"qoriq-clk: could not get parent node\\n\");\n" "> return;\n" "> }\n" - "> =\n" - "\n" - "> @@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __init=\n" - "const =3D {\n" + "> \n" + "> @@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] __initconst = {\n" "> {}\n" "> };\n" - "> =\n" - "\n" + "> \n" "> -static int __init ppc_corenet_clk_probe(struct platform_device *pdev)\n" "> +static int __init qoriq_clk_probe(struct platform_device *pdev)\n" "> {\n" "> of_clk_init(clk_match);\n" - "> =\n" - "\n" + "> \n" "> return 0;\n" "> }\n" - "> =\n" - "\n" - "> -static const struct of_device_id ppc_clk_ids[] __initconst =3D {\n" - "> +static const struct of_device_id qoriq_clk_ids[] __initconst =3D {\n" - "> { .compatible =3D \"fsl,qoriq-clockgen-1.0\", },\n" - "> { .compatible =3D \"fsl,qoriq-clockgen-2.0\", },\n" + "> \n" + "> -static const struct of_device_id ppc_clk_ids[] __initconst = {\n" + "> +static const struct of_device_id qoriq_clk_ids[] __initconst = {\n" + "> { .compatible = \"fsl,qoriq-clockgen-1.0\", },\n" + "> { .compatible = \"fsl,qoriq-clockgen-2.0\", },\n" "> {}\n" "> };\n" - "> =\n" - "\n" - "> -static struct platform_driver ppc_corenet_clk_driver __initdata =3D {\n" - "> +static struct platform_driver qoriq_clk_driver __initdata =3D {\n" - "> .driver =3D {\n" - "> - .name =3D \"ppc_corenet_clock\",\n" - "> + .name =3D \"qoriq_clock\",\n" - "> .owner =3D THIS_MODULE,\n" - "> - .of_match_table =3D ppc_clk_ids,\n" - "> + .of_match_table =3D qoriq_clk_ids,\n" + "> \n" + "> -static struct platform_driver ppc_corenet_clk_driver __initdata = {\n" + "> +static struct platform_driver qoriq_clk_driver __initdata = {\n" + "> .driver = {\n" + "> - .name = \"ppc_corenet_clock\",\n" + "> + .name = \"qoriq_clock\",\n" + "> .owner = THIS_MODULE,\n" + "> - .of_match_table = ppc_clk_ids,\n" + "> + .of_match_table = qoriq_clk_ids,\n" "> },\n" - "> - .probe =3D ppc_corenet_clk_probe,\n" - "> + .probe =3D qoriq_clk_probe,\n" + "> - .probe = ppc_corenet_clk_probe,\n" + "> + .probe = qoriq_clk_probe,\n" "> };\n" - "> =\n" - "\n" + "> \n" "> -static int __init ppc_corenet_clk_init(void)\n" "> +static int __init qoriq_clk_init(void)\n" "> {\n" @@ -157,23 +128,18 @@ "> -subsys_initcall(ppc_corenet_clk_init);\n" "> +subsys_initcall(qoriq_clk_init);\n" "> +\n" - "> +CLK_OF_DECLARE(qoriq_core_pll_v1, \"fsl,qoriq-core-pll-1.0\", core_pll_ini=\n" - "t);\n" - "> +CLK_OF_DECLARE(qoriq_core_pll_v2, \"fsl,qoriq-core-pll-2.0\", core_pll_ini=\n" - "t);\n" - "> +CLK_OF_DECLARE(qoriq_core_mux_v1, \"fsl,qoriq-core-mux-1.0\", core_mux_ini=\n" - "t);\n" - "> +CLK_OF_DECLARE(qoriq_core_mux_v2, \"fsl,qoriq-core-mux-2.0\", core_mux_ini=\n" - "t);\n" + "> +CLK_OF_DECLARE(qoriq_core_pll_v1, \"fsl,qoriq-core-pll-1.0\", core_pll_init);\n" + "> +CLK_OF_DECLARE(qoriq_core_pll_v2, \"fsl,qoriq-core-pll-2.0\", core_pll_init);\n" + "> +CLK_OF_DECLARE(qoriq_core_mux_v1, \"fsl,qoriq-core-mux-1.0\", core_mux_init);\n" + "> +CLK_OF_DECLARE(qoriq_core_mux_v2, \"fsl,qoriq-core-mux-2.0\", core_mux_init);\n" "\n" "Is there binding documentation for these compatibles?\n" "\n" "Regards,\n" "Mike\n" "\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.8.0\n" - >=20 + > -5d08394dc5b15720b56d007e93532f6c5c6d112e6e5ae198039d22a3f5dc288c +0eef94f2c657c24e1807b32d5c3089c2cef1b4b18549c98bf7edb91922d1ebed
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