From: Dave Jones <davej@redhat.com>
To: "Bryan O'Donoghue" <pure.logic@nexus-software.ie>
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/1] x86: Quark: Enable correct cache size/type reporting
Date: Mon, 29 Sep 2014 09:40:08 -0400 [thread overview]
Message-ID: <20140929134008.GA7764@redhat.com> (raw)
In-Reply-To: <1411956372-16469-2-git-send-email-pure.logic@nexus-software.ie>
On Mon, Sep 29, 2014 at 03:06:12AM +0100, Bryan O'Donoghue wrote:
> Quark X1000 lacks cpuid(4). It has cpuid(2) but returns no cache
> descriptors we can work with i.e. cpuid(2) returns
> eax=0x00000001 ebx=0x00000000 ecx=0x00000000 edx=0x00000000
>
> Quark X1000 contains a 16k 4-way set associative unified L1 cache
> with 256 sets
>
> This patch emulates cpuid(4) in a similar way to other x86
> processors like AMDs which don't support cpuid(4). The Quark code
> is based on the existing AMD code.
This looks like it would work, but I wonder if it would be a lot
simpler to do something like what we do in centaur_size_cache()
which is the other case I recall where we had to override
the CPUs definition of cache size.
Dave
next prev parent reply other threads:[~2014-09-29 13:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-29 2:06 [PATCH 0/1] x86: Quark: Enable correct cache size/type reporting Bryan O'Donoghue
2014-09-29 2:06 ` [PATCH 1/1] " Bryan O'Donoghue
2014-09-29 12:15 ` Ingo Molnar
2014-09-29 12:22 ` Bryan O'Donoghue
2014-09-29 12:34 ` Ingo Molnar
2014-09-29 12:35 ` Bryan O'Donoghue
2014-09-29 13:40 ` Dave Jones [this message]
2014-09-29 14:11 ` Bryan O'Donoghue
2014-09-29 14:17 ` Ingo Molnar
2014-09-29 14:18 ` Bryan O'Donoghue
2014-09-29 12:17 ` [PATCH 0/1] " Ingo Molnar
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