diff for duplicates of <20141001112332.GB13759@leverpostej> diff --git a/a/1.txt b/N1/1.txt index 1976cb0..2725176 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,10 +1,10 @@ -On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra at gmail.com wrote: -> From: "zhizhou.zhang" <zhizhou.zhang@spreadtrum.com> +On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: +> From: "zhizhou.zhang" <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> > > Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture. > -> Signed-off-by: zhizhou.zhang <zhizhou.zhang@spreadtrum.com> -> Signed-off-by: chunyan.zhang <chunyan.zhang@spreadtrum.com> +> Signed-off-by: zhizhou.zhang <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> +> Signed-off-by: chunyan.zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> > --- > arch/arm64/boot/dts/sprd_shark64.dts | 110 ++++++++++++++++++++++++++++++++++ > 1 file changed, 110 insertions(+) @@ -58,7 +58,7 @@ Can we not use stdout-path for this? > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; @@ -76,21 +76,21 @@ If you must use spin-table, please give each CPU a unique release address. > + }; -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 2 { +> + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 3 { +> + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x3>; @@ -99,7 +99,7 @@ address. > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0 0x80000000 0 0x20000000>; > + }; @@ -112,7 +112,7 @@ address. Could you move this up above chosen, please? > + -> + gic: interrupt-controller at 12001000 { +> + gic: interrupt-controller@12001000 { > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -130,7 +130,7 @@ work in your bootloader. > + }; > + -> + intc:interrupt-controller at 71400000 { +> + intc:interrupt-controller@71400000 { > + compatible = "sprd,intc"; > + #interrupt-cells = <0>; > + interrupt-controller; @@ -159,7 +159,7 @@ get rid of the clock-frequency property here. > + }; > + -> + uart0: uart at 70000000 { +> + uart0: uart@70000000 { > + compatible = "sprd,serial"; > + reg = <0 0x70000000 0 0x100>; > + interrupts = <0 2 0xf04>; @@ -170,7 +170,7 @@ No clocks/dmas/etc necessary? Mark. > + -> + uart1: uart at 70100000 { +> + uart1: uart@70100000 { > + compatible = "sprd,serial"; > + reg = <0 0x70100000 0 0x100>; > + interrupts = <0 3 0xf04>; @@ -179,4 +179,8 @@ Mark. > -- > 1.7.9.5 > -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 9af9ad5..34beb4c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,37 @@ "ref\01411992293-7729-1-git-send-email-zhang.lyra@gmail.com\0" "ref\01411992293-7729-3-git-send-email-zhang.lyra@gmail.com\0" - "From\0mark.rutland@arm.com (Mark Rutland)\0" - "Subject\0[PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" + "ref\01411992293-7729-3-git-send-email-zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" "Date\0Wed, 1 Oct 2014 12:23:33 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0Catalin Marinas <Catalin.Marinas-5wv7dgnIgG8@public.gmane.org>" + gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org> + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + jslaby-AlSwsSmVLrQ@public.gmane.org <jslaby-AlSwsSmVLrQ@public.gmane.org> + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org <broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + m-karicheri2-l0cyMroinI0@public.gmane.org <m-karicheri2-l0cyMroinI0@public.gmane.org> + Pawel Moll <Pawel.Moll-5wv7dgnIgG8@public.gmane.org> + artagnon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <artagnon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + rrichter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org <rrichter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org> + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Will Deacon <Will.Deacon-5wv7dgnIgG8@public.gmane.org> + orsonzhai-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <orsonzhai-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + geng.ren-lxIno14LUO0EEoCn2XhGlw@public.gmane.org <geng.ren-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> + zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kern>\0" "\00:1\0" "b\0" - "On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra at gmail.com wrote:\n" - "> From: \"zhizhou.zhang\" <zhizhou.zhang@spreadtrum.com>\n" + "On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:\n" + "> From: \"zhizhou.zhang\" <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" "> \n" "> Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture.\n" "> \n" - "> Signed-off-by: zhizhou.zhang <zhizhou.zhang@spreadtrum.com>\n" - "> Signed-off-by: chunyan.zhang <chunyan.zhang@spreadtrum.com>\n" + "> Signed-off-by: zhizhou.zhang <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" + "> Signed-off-by: chunyan.zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" "> ---\n" "> arch/arm64/boot/dts/sprd_shark64.dts | 110 ++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 110 insertions(+)\n" @@ -66,7 +85,7 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "\n" @@ -84,21 +103,21 @@ "address.\n" "\n" "> +\t\t};\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -107,7 +126,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0 0x80000000 0 0x20000000>;\n" "> +\t};\n" @@ -120,7 +139,7 @@ "Could you move this up above chosen, please?\n" "\n" "> +\n" - "> +\tgic: interrupt-controller at 12001000 {\n" + "> +\tgic: interrupt-controller@12001000 {\n" "> +\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -138,7 +157,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tintc:interrupt-controller at 71400000 {\n" + "> +\tintc:interrupt-controller@71400000 {\n" "> +\t\tcompatible = \"sprd,intc\";\n" "> +\t\t#interrupt-cells = <0>;\n" "> +\t\tinterrupt-controller;\n" @@ -167,7 +186,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tuart0: uart at 70000000 {\n" + "> +\tuart0: uart@70000000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70000000 0 0x100>;\n" "> +\t\tinterrupts = <0 2 0xf04>;\n" @@ -178,7 +197,7 @@ "Mark.\n" "\n" "> +\n" - "> +\tuart1: uart at 70100000 {\n" + "> +\tuart1: uart@70100000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70100000 0 0x100>;\n" "> +\t\tinterrupts = <0 3 0xf04>;\n" @@ -187,6 +206,10 @@ "> -- \n" "> 1.7.9.5\n" "> \n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -b25b08a86e077a2e5a4107d3ded3e03ca727d410a3dafe7744f12b0638c9c498 +19f4d8d026797a7aaf12b14560d2cfceb5950c5d1245ee7af2662d405e96d47f
diff --git a/a/1.txt b/N2/1.txt index 1976cb0..24ed480 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra at gmail.com wrote: +On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra@gmail.com wrote: > From: "zhizhou.zhang" <zhizhou.zhang@spreadtrum.com> > > Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture. @@ -58,7 +58,7 @@ Can we not use stdout-path for this? > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; @@ -76,21 +76,21 @@ If you must use spin-table, please give each CPU a unique release address. > + }; -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 2 { +> + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 3 { +> + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x3>; @@ -99,7 +99,7 @@ address. > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0 0x80000000 0 0x20000000>; > + }; @@ -112,7 +112,7 @@ address. Could you move this up above chosen, please? > + -> + gic: interrupt-controller at 12001000 { +> + gic: interrupt-controller@12001000 { > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -130,7 +130,7 @@ work in your bootloader. > + }; > + -> + intc:interrupt-controller at 71400000 { +> + intc:interrupt-controller@71400000 { > + compatible = "sprd,intc"; > + #interrupt-cells = <0>; > + interrupt-controller; @@ -159,7 +159,7 @@ get rid of the clock-frequency property here. > + }; > + -> + uart0: uart at 70000000 { +> + uart0: uart@70000000 { > + compatible = "sprd,serial"; > + reg = <0 0x70000000 0 0x100>; > + interrupts = <0 2 0xf04>; @@ -170,7 +170,7 @@ No clocks/dmas/etc necessary? Mark. > + -> + uart1: uart at 70100000 { +> + uart1: uart@70100000 { > + compatible = "sprd,serial"; > + reg = <0 0x70100000 0 0x100>; > + interrupts = <0 3 0xf04>; diff --git a/a/content_digest b/N2/content_digest index 9af9ad5..9e27088 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,31 @@ "ref\01411992293-7729-1-git-send-email-zhang.lyra@gmail.com\0" "ref\01411992293-7729-3-git-send-email-zhang.lyra@gmail.com\0" - "From\0mark.rutland@arm.com (Mark Rutland)\0" - "Subject\0[PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" + "From\0Mark Rutland <mark.rutland@arm.com>\0" + "Subject\0Re: [PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" "Date\0Wed, 1 Oct 2014 12:23:33 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0zhang.lyra@gmail.com <zhang.lyra@gmail.com>\0" + "Cc\0Catalin Marinas <Catalin.Marinas@arm.com>" + gregkh@linuxfoundation.org <gregkh@linuxfoundation.org> + ijc+devicetree@hellion.org.uk <ijc+devicetree@hellion.org.uk> + jslaby@suse.cz <jslaby@suse.cz> + galak@codeaurora.org <galak@codeaurora.org> + broonie@linaro.org <broonie@linaro.org> + m-karicheri2@ti.com <m-karicheri2@ti.com> + Pawel Moll <Pawel.Moll@arm.com> + artagnon@gmail.com <artagnon@gmail.com> + rrichter@cavium.com <rrichter@cavium.com> + robh+dt@kernel.org <robh+dt@kernel.org> + Will Deacon <Will.Deacon@arm.com> + orsonzhai@gmail.com <orsonzhai@gmail.com> + geng.ren@spreadtrum.com <geng.ren@spreadtrum.com> + zhizhou.zhang@spreadtrum.com <zhizhou.zhang@spreadtrum.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + " chunyan.zhang <chunyan.zhang@spreadtrum.com>\0" "\00:1\0" "b\0" - "On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra at gmail.com wrote:\n" + "On Mon, Sep 29, 2014 at 01:04:49PM +0100, zhang.lyra@gmail.com wrote:\n" "> From: \"zhizhou.zhang\" <zhizhou.zhang@spreadtrum.com>\n" "> \n" "> Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture.\n" @@ -66,7 +85,7 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "\n" @@ -84,21 +103,21 @@ "address.\n" "\n" "> +\t\t};\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -107,7 +126,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0 0x80000000 0 0x20000000>;\n" "> +\t};\n" @@ -120,7 +139,7 @@ "Could you move this up above chosen, please?\n" "\n" "> +\n" - "> +\tgic: interrupt-controller at 12001000 {\n" + "> +\tgic: interrupt-controller@12001000 {\n" "> +\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -138,7 +157,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tintc:interrupt-controller at 71400000 {\n" + "> +\tintc:interrupt-controller@71400000 {\n" "> +\t\tcompatible = \"sprd,intc\";\n" "> +\t\t#interrupt-cells = <0>;\n" "> +\t\tinterrupt-controller;\n" @@ -167,7 +186,7 @@ "\n" "> +\t};\n" "> +\n" - "> +\tuart0: uart at 70000000 {\n" + "> +\tuart0: uart@70000000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70000000 0 0x100>;\n" "> +\t\tinterrupts = <0 2 0xf04>;\n" @@ -178,7 +197,7 @@ "Mark.\n" "\n" "> +\n" - "> +\tuart1: uart at 70100000 {\n" + "> +\tuart1: uart@70100000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70100000 0 0x100>;\n" "> +\t\tinterrupts = <0 3 0xf04>;\n" @@ -189,4 +208,4 @@ "> \n" > -b25b08a86e077a2e5a4107d3ded3e03ca727d410a3dafe7744f12b0638c9c498 +0571e9b2f394ec4fe2584415fa29e472cad03c87b08533c1c9edce984745993e
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