From mboxrd@z Thu Jan 1 00:00:00 1970 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Subject: Re: [PATCH 1/6] KVM: x86: DR7.GD should be cleared upon any #DB exception Date: Wed, 1 Oct 2014 17:24:46 +0200 Message-ID: <20141001152446.GA12085@potion.brq.redhat.com> References: <1412099359-5316-1-git-send-email-namit@cs.technion.ac.il> <1412099359-5316-2-git-send-email-namit@cs.technion.ac.il> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: pbonzini@redhat.com, kvm@vger.kernel.org, nadav.amit@gmail.com To: Nadav Amit Return-path: Received: from mx1.redhat.com ([209.132.183.28]:58123 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750992AbaJAPYz (ORCPT ); Wed, 1 Oct 2014 11:24:55 -0400 Content-Disposition: inline In-Reply-To: <1412099359-5316-2-git-send-email-namit@cs.technion.ac.il> Sender: kvm-owner@vger.kernel.org List-ID: 2014-09-30 20:49+0300, Nadav Amit: > Intel SDM 17.2.4 (Debug Control Register (DR7)) says: "The processor = clears the > GD flag upon entering to the debug exception handler." This sentence = may be > misunderstood as if it happens only on #DB due to debug-register prot= ection, > but it happens regardless to the cause of the #DB. All real hardware behaves that way? Intel has another sentence after that [...], to allow the handler access to the debug registers. I suppose that the "the" is important, but I haven't verified it.[1] Clearing GD on every #DB would also make the stated purpose[2] harder t= o achieve without adding any benefit; it seems like a bug for Intel. --- 1: AMD [13.1.1.4 Debug-Control Register (DR7)] uses a similar wording General-Detect Enable (GD)=E2=80=94Bit 13. Software sets this bit = to 1 to cause a debug exception to occur when an attempt is made to execut= e a MOV DRn instruction to any debug register (DR0=E2=80=93DR7). Thi= s bit is cleared to 0 by the processor when the #DB handler is entered, allowing the handler to read and write the DRn registers. The #DB exception occurs before executing the instruction, and DR6[BD] is set by the processor. Software debuggers can use this bit to prevent the currently-executing program from interfering with the debug operation. 2: Last sentence of [1] and also this from Intel This condition is provided to support in-circuit emulators. When the emulator needs to access the debug registers, emulator software can set the GD flag to prevent interference from the program currently executing on the processor.