From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gleb Natapov Subject: Re: [RFC] vPMU support for AMD system Date: Sat, 4 Oct 2014 10:00:16 +0300 Message-ID: <20141004070016.GR26540@minantech.com> References: <542B61DA.3070307@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Cc: pbonzini@redhat.com, KVM To: Wei Huang Return-path: Received: from mail-wg0-f45.google.com ([74.125.82.45]:40793 "EHLO mail-wg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751112AbaJDHAU (ORCPT ); Sat, 4 Oct 2014 03:00:20 -0400 Received: by mail-wg0-f45.google.com with SMTP id m15so2995732wgh.28 for ; Sat, 04 Oct 2014 00:00:19 -0700 (PDT) Content-Disposition: inline In-Reply-To: <542B61DA.3070307@redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: Hi, On Tue, Sep 30, 2014 at 09:07:22PM -0500, Wei Huang wrote: > Hi Paolo and Gleb, > > The attached file is a preliminary version of AMD vPMU support for KVM. > Currently I am working on a formal patch set; but realized that there are > some design choice to make (see below). I thought it is better to send it > out now, asking for your comments before sending out patchset v1. > > If you are OK with current approach, please let me know. Otherwise please > share your suggestions/comments on the design choice (see suggestions > below). I will send out split patch set soon. > I am not very familiar with AMD PMU, but IIRC is lacks architectural PMU, so the first question that comes to my mind is: > +static struct kvm_event_hw_type_mapping amd_event_mapping[] = { > + [0] = { 0x76, 0x00, PERF_COUNT_HW_CPU_CYCLES }, > + [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS }, > + [3] = { 0x80, 0x00, PERF_COUNT_HW_CACHE_REFERENCES }, > + [4] = { 0x81, 0x00, PERF_COUNT_HW_CACHE_MISSES }, > + [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS }, > + [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES }, > +}; > + Are those evens count exactly same things on all AMD cpus? -- Gleb.