diff for duplicates of <20141006122856.GB26833@ulmo>

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diff --git a/a/1.2.hdr b/a/1.2.hdr
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diff --git a/a/1.1.txt b/N1/1.txt
similarity index 88%
rename from a/1.1.txt
rename to N1/1.txt
index 5eb45c8..92af6f6 100644
--- a/a/1.1.txt
+++ b/N1/1.txt
@@ -32,8 +32,8 @@ Indeed so.
 > 
 > "Due to the comparison mechanism, the output pulse has a width between
 > zero and 255 PWM counter cycles. Thus by adding a simple passive filter
-> outside the chip, an analog voltage between 0 and (255/256) × VDD can
-> be obtained (for the positive polarity case, or between (1/256) × VDD
+> outside the chip, an analog voltage between 0 and (255/256) ? VDD can
+> be obtained (for the positive polarity case, or between (1/256) ? VDD
 > and VDD for the negative polarity case). Other voltage values can be
 > obtained by adding active external circuitry."
 > 
@@ -72,7 +72,7 @@ in a comment to clarify.
 > Quote from the datasheet:
 > 
 > "
-> • PWMPOL: LCD Controller PWM Signal Polarity
+> ? PWMPOL: LCD Controller PWM Signal Polarity
 > This bit defines the polarity of the PWM output signal. If set to one,
 > the output pulses are high level (the output will be high when- ever
 > the value in the counter is less than the value CVAL) If set to zero,
@@ -85,3 +85,10 @@ in a comment to clarify.
 Yes, sounds good then.
 
 Thierry
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diff --git a/a/2.hdr b/a/2.hdr
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diff --git a/a/2.txt b/a/2.txt
deleted file mode 100644
index e61f46a..0000000
--- a/a/2.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-_______________________________________________
-dri-devel mailing list
-dri-devel@lists.freedesktop.org
-http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/a/content_digest b/N1/content_digest
index 1c990ae..a52323e 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,28 +2,11 @@
  "ref\01412175188-28278-4-git-send-email-boris.brezillon@free-electrons.com\0"
  "ref\020141006104634.GE25202@ulmo\0"
  "ref\020141006135009.6cd980a1@bbrezillon\0"
- "From\0Thierry Reding <thierry.reding@gmail.com>\0"
- "Subject\0Re: [PATCH v7 03/11] pwm: add support for atmel-hlcdc-pwm device\0"
+ "From\0thierry.reding@gmail.com (Thierry Reding)\0"
+ "Subject\0[PATCH v7 03/11] pwm: add support for atmel-hlcdc-pwm device\0"
  "Date\0Mon, 6 Oct 2014 14:28:57 +0200\0"
- "To\0Boris Brezillon <boris.brezillon@free-electrons.com>\0"
- "Cc\0Mark Rutland <mark.rutland@arm.com>"
-  linux-pwm@vger.kernel.org
-  devicetree@vger.kernel.org
-  Samuel Ortiz <sameo@linux.intel.com>
-  Pawel Moll <pawel.moll@arm.com>
-  Ian Campbell <ijc+devicetree@hellion.org.uk>
-  Lee Jones <lee.jones@linaro.org>
-  Nicolas Ferre <nicolas.ferre@atmel.com>
-  linux-kernel@vger.kernel.org
-  dri-devel@lists.freedesktop.org
-  Rob Herring <robh+dt@kernel.org>
-  Alexandre Belloni <alexandre.belloni@free-electrons.com>
-  Kumar Gala <galak@codeaurora.org>
-  Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
-  Andrew Victor <linux@maxim.org.za>
-  linux-arm-kernel@lists.infradead.org
- " Mark Yao <mark.yao@rock-chips.com>\0"
- "\02:1.1\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
+ "\00:1\0"
  "b\0"
  "On Mon, Oct 06, 2014 at 01:50:09PM +0200, Boris Brezillon wrote:\n"
  "> On Mon, 6 Oct 2014 12:46:35 +0200 Thierry Reding <thierry.reding@gmail.com> wrote:\n"
@@ -59,8 +42,8 @@
  "> \n"
  "> \"Due to the comparison mechanism, the output pulse has a width between\n"
  "> zero and 255 PWM counter cycles. Thus by adding a simple passive filter\n"
- "> outside the chip, an analog voltage between 0 and (255/256) \303\227 VDD can\n"
- "> be obtained (for the positive polarity case, or between (1/256) \303\227 VDD\n"
+ "> outside the chip, an analog voltage between 0 and (255/256) ? VDD can\n"
+ "> be obtained (for the positive polarity case, or between (1/256) ? VDD\n"
  "> and VDD for the negative polarity case). Other voltage values can be\n"
  "> obtained by adding active external circuitry.\"\n"
  "> \n"
@@ -99,7 +82,7 @@
  "> Quote from the datasheet:\n"
  "> \n"
  "> \"\n"
- "> \342\200\242 PWMPOL: LCD Controller PWM Signal Polarity\n"
+ "> ? PWMPOL: LCD Controller PWM Signal Polarity\n"
  "> This bit defines the polarity of the PWM output signal. If set to one,\n"
  "> the output pulses are high level (the output will be high when- ever\n"
  "> the value in the counter is less than the value CVAL) If set to zero,\n"
@@ -111,31 +94,13 @@
  "\n"
  "Yes, sounds good then.\n"
  "\n"
- Thierry
- "\02:1.2\0"
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- "_______________________________________________\n"
- "dri-devel mailing list\n"
- "dri-devel@lists.freedesktop.org\n"
- http://lists.freedesktop.org/mailman/listinfo/dri-devel
+ "Thierry\n"
+ "-------------- next part --------------\n"
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