diff for duplicates of <20141010134534.GC6004@leverpostej> diff --git a/a/1.txt b/N1/1.txt index 7ce443a..28703c5 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,6 +1,6 @@ Hi Suravee, -On Sun, Sep 28, 2014 at 09:53:27PM +0100, suravee.suthikulpanit@amd.com wrote: +On Sun, Sep 28, 2014 at 09:53:27PM +0100, suravee.suthikulpanit at amd.com wrote: > From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> > > Initial revision of device tree for AMD Seattle platform @@ -107,7 +107,7 @@ use those properties anyway. > + clock-output-names = "uartspiclk_100mhz"; > + }; > + -> + dma0: dma@1,0500000 { +> + dma0: dma at 1,0500000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0 0x0500000 0 0x1000>; > + interrupts = @@ -128,7 +128,7 @@ I didn't spot an SMMU, so I think this should go. > + }; > + -> + sata0: sata@1,00300000 { +> + sata0: sata at 1,00300000 { > + compatible = "snps,spear-ahci"; > + reg = <0 0x300000 0 0x800>; > + interrupts = <0 355 4>; @@ -141,7 +141,7 @@ Likewise. > + dma-coherent; > + }; > + -> + i2c@1,1000000 { +> + i2c at 1,1000000 { > + compatible = "snps,designware-i2c"; > + reg = <0 0x01000000 0 0x1000>; > + interrupts = <0 357 4>; @@ -149,7 +149,7 @@ Likewise. > + clock-names = "apb_pclk"; > + }; > + -> + v2m_serial0: uart@1,1010000 { +> + v2m_serial0: uart at 1,1010000 { > + compatible = "arm,pl011", "arm,primecell"; > + reg = <0 0x1010000 0 0x1000>; > + interrupts = <0 328 4>; @@ -157,7 +157,7 @@ Likewise. > + clock-names = "uartclk", "apb_pclk"; > + }; > + -> + ssp@1,1020000 { +> + ssp at 1,1020000 { > + #gpio-cells = <2>; > + compatible = "arm,pl022", "arm,primecell"; @@ -170,7 +170,7 @@ Please put the compatible property first in each node. > + clock-names = "apb_pclk"; > + }; > + -> + ssp@1,1030000 { +> + ssp at 1,1030000 { > + #gpio-cells = <2>; > + compatible = "arm,pl022", "arm,primecell"; > + reg = <0 0x1030000 0 0x1000>; @@ -182,7 +182,7 @@ Please put the compatible property first in each node. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + sdcard@1 { +> + sdcard at 1 { > + compatible = "mmc-spi-slot"; > + reg = <0>; @@ -197,7 +197,7 @@ The unit-address should match the first reg entry. > + }; > + }; > + -> + gpio@1,1040000 { +> + gpio at 1,1040000 { > + #gpio-cells = <2>; > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0 0x1040000 0 0x1000>; @@ -207,7 +207,7 @@ The unit-address should match the first reg entry. > + clock-names = "apb_pclk"; > + }; > + -> + gpio@1,1050000 { +> + gpio at 1,1050000 { > + #gpio-cells = <2>; > + compatible = "arm,pl061", "arm,primecell"; > + reg = <0 0x1050000 0 0x1000>; @@ -217,7 +217,7 @@ The unit-address should match the first reg entry. > + clock-names = "apb_pclk"; > + }; > + -> + timer@1,1060000 { +> + timer at 1,1060000 { > + compatible = "arm,standalone_a5_twd"; > + reg = <0 0x1060000 0 0x40>; > + interrupts = @@ -228,7 +228,7 @@ The unit-address should match the first reg entry. This binding does not exist in mainline. > + -> + ccp: ccp@1,00100000 { +> + ccp: ccp at 1,00100000 { > + compatible = "amd,ccp-seattle-v1a"; > + reg = <0 0x00100000 0 0x10000>; > + interrupts = <0 3 4>; @@ -316,7 +316,7 @@ In what way is this modified? > + }; > + }; > + /* Cluster 0 Core 0 */ -> + CPU0: cpu@0 { +> + CPU0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; @@ -331,7 +331,7 @@ Not PSCI? > + }; > + > + /* Cluster 0 Core 1 */ -> + CPU1: cpu@1 { +> + CPU1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0001>; @@ -346,7 +346,7 @@ At least the release addresses are unique... > + > + /* Note: This entry is modified by UEFI */ -> + memory@8000000000 { +> + memory at 8000000000 { > + device_type = "memory"; > + reg = <0x00000080 0x00000000 0x1 0x00000000>; /* 4GB */ > + }; @@ -357,7 +357,7 @@ map. How exactly does UEFI modify this? > + -> + gic: interrupt-controller@e1101000 { +> + gic: interrupt-controller at e1101000 { > + compatible = "arm,gic-400", "arm,cortex-a15-gic"; > + #interrupt-cells = <3>; > + #address-cells = <2>; @@ -376,7 +376,7 @@ The comments are confusing, because they don't match the architected names. I would drop them. > + interrupts = <1 8 0xf04>; -> + v2m0: v2m@0x8000 { +> + v2m0: v2m at 0x8000 { > + compatible = "arm,gic-v2m-frame"; > + msi-controller; > + arm,msi-base-spi = <64>; diff --git a/a/content_digest b/N1/content_digest index 16d6a14..dd26933 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,29 +1,14 @@ "ref\01411937610-22125-1-git-send-email-suravee.suthikulpanit@amd.com\0" "ref\01411937610-22125-2-git-send-email-suravee.suthikulpanit@amd.com\0" - "From\0Mark Rutland <mark.rutland@arm.com>\0" - "Subject\0Re: [RFC 1/4] arm64: amd-seattle: Adding device tree for AMD Seattle platform\0" + "From\0mark.rutland@arm.com (Mark Rutland)\0" + "Subject\0[RFC 1/4] arm64: amd-seattle: Adding device tree for AMD Seattle platform\0" "Date\0Fri, 10 Oct 2014 14:45:34 +0100\0" - "To\0suravee.suthikulpanit@amd.com <suravee.suthikulpanit@amd.com>\0" - "Cc\0Will Deacon <Will.Deacon@arm.com>" - Liviu Dudau <Liviu.Dudau@arm.com> - Marc Zyngier <Marc.Zyngier@arm.com> - Catalin Marinas <Catalin.Marinas@arm.com> - jason@lakedaemon.net <jason@lakedaemon.net> - tglx@linutronix.de <tglx@linutronix.de> - robh+dt@kernel.org <robh+dt@kernel.org> - bhelgaas@google.com <bhelgaas@google.com> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> - linux-pci@vger.kernel.org <linux-pci@vger.kernel.org> - linux-doc@vger.kernel.org <linux-doc@vger.kernel.org> - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - Thomas Lendacky <Thomas.Lendacky@amd.com> - " Joel Schopp <Joel.Schopp@amd.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Suravee,\n" "\n" - "On Sun, Sep 28, 2014 at 09:53:27PM +0100, suravee.suthikulpanit@amd.com wrote:\n" + "On Sun, Sep 28, 2014 at 09:53:27PM +0100, suravee.suthikulpanit at amd.com wrote:\n" "> From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>\n" ">\n" "> Initial revision of device tree for AMD Seattle platform\n" @@ -130,7 +115,7 @@ "> + clock-output-names = \"uartspiclk_100mhz\";\n" "> + };\n" "> +\n" - "> + dma0: dma@1,0500000 {\n" + "> + dma0: dma at 1,0500000 {\n" "> + compatible = \"arm,pl330\", \"arm,primecell\";\n" "> + reg = <0 0x0500000 0 0x1000>;\n" "> + interrupts =\n" @@ -151,7 +136,7 @@ "\n" "> + };\n" "> +\n" - "> + sata0: sata@1,00300000 {\n" + "> + sata0: sata at 1,00300000 {\n" "> + compatible = \"snps,spear-ahci\";\n" "> + reg = <0 0x300000 0 0x800>;\n" "> + interrupts = <0 355 4>;\n" @@ -164,7 +149,7 @@ "> + dma-coherent;\n" "> + };\n" "> +\n" - "> + i2c@1,1000000 {\n" + "> + i2c at 1,1000000 {\n" "> + compatible = \"snps,designware-i2c\";\n" "> + reg = <0 0x01000000 0 0x1000>;\n" "> + interrupts = <0 357 4>;\n" @@ -172,7 +157,7 @@ "> + clock-names = \"apb_pclk\";\n" "> + };\n" "> +\n" - "> + v2m_serial0: uart@1,1010000 {\n" + "> + v2m_serial0: uart at 1,1010000 {\n" "> + compatible = \"arm,pl011\", \"arm,primecell\";\n" "> + reg = <0 0x1010000 0 0x1000>;\n" "> + interrupts = <0 328 4>;\n" @@ -180,7 +165,7 @@ "> + clock-names = \"uartclk\", \"apb_pclk\";\n" "> + };\n" "> +\n" - "> + ssp@1,1020000 {\n" + "> + ssp at 1,1020000 {\n" "> + #gpio-cells = <2>;\n" "> + compatible = \"arm,pl022\", \"arm,primecell\";\n" "\n" @@ -193,7 +178,7 @@ "> + clock-names = \"apb_pclk\";\n" "> + };\n" "> +\n" - "> + ssp@1,1030000 {\n" + "> + ssp at 1,1030000 {\n" "> + #gpio-cells = <2>;\n" "> + compatible = \"arm,pl022\", \"arm,primecell\";\n" "> + reg = <0 0x1030000 0 0x1000>;\n" @@ -205,7 +190,7 @@ "> + #address-cells = <1>;\n" "> + #size-cells = <0>;\n" "> +\n" - "> + sdcard@1 {\n" + "> + sdcard at 1 {\n" "> + compatible = \"mmc-spi-slot\";\n" "> + reg = <0>;\n" "\n" @@ -220,7 +205,7 @@ "> + };\n" "> + };\n" "> +\n" - "> + gpio@1,1040000 {\n" + "> + gpio at 1,1040000 {\n" "> + #gpio-cells = <2>;\n" "> + compatible = \"arm,pl061\", \"arm,primecell\";\n" "> + reg = <0 0x1040000 0 0x1000>;\n" @@ -230,7 +215,7 @@ "> + clock-names = \"apb_pclk\";\n" "> + };\n" "> +\n" - "> + gpio@1,1050000 {\n" + "> + gpio at 1,1050000 {\n" "> + #gpio-cells = <2>;\n" "> + compatible = \"arm,pl061\", \"arm,primecell\";\n" "> + reg = <0 0x1050000 0 0x1000>;\n" @@ -240,7 +225,7 @@ "> + clock-names = \"apb_pclk\";\n" "> + };\n" "> +\n" - "> + timer@1,1060000 {\n" + "> + timer at 1,1060000 {\n" "> + compatible = \"arm,standalone_a5_twd\";\n" "> + reg = <0 0x1060000 0 0x40>;\n" "> + interrupts =\n" @@ -251,7 +236,7 @@ "This binding does not exist in mainline.\n" "\n" "> +\n" - "> + ccp: ccp@1,00100000 {\n" + "> + ccp: ccp at 1,00100000 {\n" "> + compatible = \"amd,ccp-seattle-v1a\";\n" "> + reg = <0 0x00100000 0 0x10000>;\n" "> + interrupts = <0 3 4>;\n" @@ -339,7 +324,7 @@ "> + };\n" "> + };\n" "> + /* Cluster 0 Core 0 */\n" - "> + CPU0: cpu@0 {\n" + "> + CPU0: cpu at 0 {\n" "> + device_type = \"cpu\";\n" "> + compatible = \"arm,armv8\";\n" "\n" @@ -354,7 +339,7 @@ "> + };\n" "> +\n" "> + /* Cluster 0 Core 1 */\n" - "> + CPU1: cpu@1 {\n" + "> + CPU1: cpu at 1 {\n" "> + device_type = \"cpu\";\n" "> + compatible = \"arm,armv8\";\n" "> + reg = <0x0 0x0001>;\n" @@ -369,7 +354,7 @@ "\n" "> +\n" "> + /* Note: This entry is modified by UEFI */\n" - "> + memory@8000000000 {\n" + "> + memory at 8000000000 {\n" "> + device_type = \"memory\";\n" "> + reg = <0x00000080 0x00000000 0x1 0x00000000>; /* 4GB */\n" "> + };\n" @@ -380,7 +365,7 @@ "How exactly does UEFI modify this?\n" "\n" "> +\n" - "> + gic: interrupt-controller@e1101000 {\n" + "> + gic: interrupt-controller at e1101000 {\n" "> + compatible = \"arm,gic-400\", \"arm,cortex-a15-gic\";\n" "> + #interrupt-cells = <3>;\n" "> + #address-cells = <2>;\n" @@ -399,7 +384,7 @@ "names. I would drop them.\n" "\n" "> + interrupts = <1 8 0xf04>;\n" - "> + v2m0: v2m@0x8000 {\n" + "> + v2m0: v2m at 0x8000 {\n" "> + compatible = \"arm,gic-v2m-frame\";\n" "> + msi-controller;\n" "> + arm,msi-base-spi = <64>;\n" @@ -456,4 +441,4 @@ "Thanks,\n" Mark. -b7ac225cac5e505e70dd96d2398aed281cb29c7164820d90851d35fc39d85c03 +1918ecaf1326cfac7f7dceaa6b9bd9306be061427cd1b24e78c1aa4d96211a7c
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