From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm: fix flush_pfn_alias
Date: Mon, 20 Oct 2014 14:43:22 +0100 [thread overview]
Message-ID: <20141020134322.GA20046@arm.com> (raw)
In-Reply-To: <2144086.KBLsLT82pe@wuerfel>
On Mon, Oct 20, 2014 at 02:39:44PM +0100, Arnd Bergmann wrote:
> On Monday 20 October 2014 21:54:02 Jungseung Lee wrote:
> > L1_CACHE_BYTES could be larger than real L1 cache line size.
> > In that case, flush_pfn_alias function would omit to flush last bytes
> > as much as L1_CACHE_BYTES - real cache line size.
>
> Can you list an example on what CPU this would happen in the
> patch description? Isn't the L1 cache line size always 32 bytes on ARM?
It's 64 bytes on A15, but I suspect it's always 32 bytes for this codepath
(VIPT aliasing D-side).
Will
next prev parent reply other threads:[~2014-10-20 13:43 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-20 12:54 [PATCH] arm: fix flush_pfn_alias Jungseung Lee
2014-10-20 13:39 ` Arnd Bergmann
2014-10-20 13:43 ` Will Deacon [this message]
2014-10-20 13:47 ` Russell King - ARM Linux
2014-10-20 15:54 ` Jungseung Lee
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