Re: [PATCH v2 16/16] usb: dwc3: enable usb suspend phy

[Felipe Balbi <balbi@ti.com>]

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Hi,

On Mon, Oct 20, 2014 at 04:41:54PM +0800, Huang Rui wrote:
> On Fri, Oct 17, 2014 at 01:48:19PM -0500, Felipe Balbi wrote:
> > Hi,
> > 
> > On Fri, Oct 17, 2014 at 06:41:04PM +0000, Paul Zimmerman wrote:
> > > > From: Felipe Balbi [mailto:balbi@ti.com]
> > > > Sent: Friday, October 17, 2014 8:00 AM
> > > > 
> > > > On Fri, Oct 17, 2014 at 04:53:41PM +0800, Huang Rui wrote:
> > > > > AMD NL needs to suspend usb3 ss phy, but this doesn't enable on simulation
> > > > > board.
> > > > >
> > > > > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > > > > ---
> > > > >  drivers/usb/dwc3/core.c          | 7 ++++++-
> > > > >  drivers/usb/dwc3/dwc3-pci.c      | 3 ++-
> > > > >  drivers/usb/dwc3/platform_data.h | 1 +
> > > > >  3 files changed, 9 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > index 3ccfe41..4a98696 100644
> > > > > --- a/drivers/usb/dwc3/core.c
> > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > @@ -395,6 +395,9 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
> > > > >  	if (dwc->quirks & DWC3_QUIRK_TX_DEEPH)
> > > > >  		reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(1);
> > > > >
> > > > > +	if (dwc->quirks & DWC3_QUIRK_SUSPHY)
> > > > 
> > > > should be:
> > > > 
> > > > 	if (!dwc->suspend_usb3_phy_quirk)
> > > > 
> > > > > +		reg |= DWC3_GUSB3PIPECTL_SUSPHY;
> > > > 
> > > > IIRC, databook asks us to set that bit anyway, so the quirk is disabling
> > > > that bit. Am I missing something ? Paul ?
> > > 
> > > It looks to me that Huang's patch is enabling that bit, not disabling
> > > it.
> > 
> > right, but that's what's actually quirky right ? IIRC, Databook asks us
> > to set usb2 and usb3 suspend phy bits and we're just not doing it.
> > 
> > > Currently the driver does not set either DWC3_GUSB3PIPECTL_SUSPHY or
> > > DWC3_GUSB2PHYCFG_SUSPHY (unless it has been added by that big patch
> > > series you just posted). According to the databook, both of those
> > > bits should be set to 1 after the core initialization has completed.
> > 
> > there you go. So unless that quirk bit flag is set, we're safe of
> > setting SUSPHY bit for everybody.
> > 
> 
> So I can update to set these two suspend phy bits defaultly in my next
> patch set, is it OK? :)

We need to split this into two patches:

patch 1 adds missing SUSPHY bit for all cores above revision 1.94a at
the end of probe()

patch 2 adds a quirk which AMD needs so that setting USB3_SUSPHY bit is
conditional on that quirk.

-- 
balbi

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