From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joe Perches Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Date: Tue, 28 Oct 2014 14:22:49 -0700 Message-ID: <1414531369.10912.14.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1414392371.8884.2.camel@perches.com> Sender: owner-linux-mm@kvack.org To: Jaroslav Kysela , Takashi Iwai Cc: "Wang, Yalin" , Russell King , linux-mm@kvack.org, Will Deacon , Akinobu Mita , linux-arm-kernel@lists.infradead.org, alsa-devel , LKML linux-mm@kvack.orgWill Deacon Akinobu Mita linux-arm-kernel@lists.infradead.orgalsa-devel LKML List-Id: alsa-devel@alsa-project.org Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; sound/usb/6fire/firmware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c index 3b02e54..62c25e7 100644 --- a/sound/usb/6fire/firmware.c +++ b/sound/usb/6fire/firmware.c @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( while (c != end) { for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++) - buffer[i] = byte_rev_table[(u8) *c]; + buffer[i] = bitrev8((u8)*c); ret = usb6fire_fw_fpga_write(device, buffer, i); if (ret < 0) { -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Wang, Yalin" Subject: RE: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Date: Wed, 29 Oct 2014 10:42:00 +0800 Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1414531369.10912.14.camel@perches.com> Content-Language: en-US Sender: owner-linux-mm@kvack.org To: 'Joe Perches' , Jaroslav Kysela , Takashi Iwai Cc: Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML "linux-mm@kvack.org" Will Deacon Akinobu Mita "linux-arm-kernel@lists.infradead.org" alsa-devel LKML List-Id: alsa-devel@alsa-project.org > Use the inline function instead of directly indexing the array. >=20 > This allows some architectures with hardware instructions for bit reversa= ls > to eliminate the array. >=20 > Signed-off-by: Joe Perches > --- > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > hardware. > [] > > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index > > > 7ffe03f..ef5b2bb 100644 > > > --- a/include/linux/bitrev.h > > > +++ b/include/linux/bitrev.h > > > @@ -3,6 +3,14 @@ > > > > > > #include > > > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > > +#include > > > + > > > +#define bitrev32 __arch_bitrev32 > > > +#define bitrev16 __arch_bitrev16 > > > +#define bitrev8 __arch_bitrev8 > > > + > > > +#else > > > extern u8 const byte_rev_table[256]; >=20 > sound/usb/6fire/firmware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c inde= x > 3b02e54..62c25e7 100644 > --- a/sound/usb/6fire/firmware.c > +++ b/sound/usb/6fire/firmware.c > @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( >=20 > while (c !=3D end) { > for (i =3D 0; c !=3D end && i < FPGA_BUFSIZE; i++, c++) > - buffer[i] =3D byte_rev_table[(u8) *c]; > + buffer[i] =3D bitrev8((u8)*c); >=20 > ret =3D usb6fire_fw_fpga_write(device, buffer, i); > if (ret < 0) { >=20 I think the most safe way is change byte_rev_table[] to be satic, So that no driver can access it directly, The build error can remind the developer if they use byte_rev_table[] Directly . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joe Perches Subject: Re: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Date: Tue, 28 Oct 2014 20:06:14 -0700 Message-ID: <1414551974.10912.16.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org To: "Wang, Yalin" Cc: Jaroslav Kysela , Takashi Iwai , Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML List-Id: alsa-devel@alsa-project.org On Wed, 2014-10-29 at 10:42 +0800, Wang, Yalin wrote: > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > > to eliminate the array. [] > > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > > hardware. [] > I think the most safe way is change byte_rev_table[] to be satic, > So that no driver can access it directly, > The build error can remind the developer if they use byte_rev_table[] > Directly . You can do that with your later patch, but the existing uses _must_ be converted first so you don't break the build. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Wang, Yalin" Subject: RE: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Date: Wed, 29 Oct 2014 11:10:08 +0800 Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825E@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> <1414551974.10912.16.camel@perches.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <1414551974.10912.16.camel@perches.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: 'Joe Perches' Cc: Jaroslav Kysela , Takashi Iwai , Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML List-Id: alsa-devel@alsa-project.org > From: Joe Perches [mailto:joe@perches.com] > > I think the most safe way is change byte_rev_table[] to be satic, So > > that no driver can access it directly, The build error can remind the > > developer if they use byte_rev_table[] Directly . > > You can do that with your later patch, but the existing uses _must_ be > converted first so you don't break the build. > > Yeah, I agree with you, I will add this into my later patch. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from smtprelay0086.hostedemail.com ([216.40.44.86]:55097 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751030AbaJ1VTE (ORCPT ); Tue, 28 Oct 2014 17:19:04 -0400 Message-ID: <1414531138.10912.12.camel@perches.com> (sfid-20141028_221928_532452_23DB8371) Subject: [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 From: Joe Perches To: Christian Lamparter Cc: "John W. Linville" , "Wang, Yalin" , Russell King , linux-mm@kvack.org, Will Deacon , Akinobu Mita , linux-arm-kernel@lists.infradead.org, linux-wireless@vger.kernel.org, netdev , LKML Date: Tue, 28 Oct 2014 14:18:58 -0700 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Sender: linux-wireless-owner@vger.kernel.org List-ID: Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; drivers/net/wireless/ath/carl9170/phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c index b80b213..dca6df1 100644 --- a/drivers/net/wireless/ath/carl9170/phy.c +++ b/drivers/net/wireless/ath/carl9170/phy.c @@ -994,7 +994,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, refsel0 = 0; refsel1 = 1; } - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } else { if (freq == 2484) { chansel = 10 + (freq - 2274) / 5; @@ -1002,7 +1002,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, } else chansel = 16 + (freq - 2272) / 5; chansel *= 4; - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } d1 = chansel; From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 24 Oct 2014 13:10:33 +0800 Subject: [PATCH RFC] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 8 ++++++++ lib/bitrev.c | 2 ++ 7 files changed, 63 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..0df5866 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index ac9afde..a2566d7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..5d24c11 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ #include +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..e0e0453 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,14 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Sun, 26 Oct 2014 23:46:11 -0700 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> Message-ID: <1414392371.8884.2.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 64 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..0df5866 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..263c28c 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -36,6 +36,7 @@ config ARM64 > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > select HAVE_ARCH_JUMP_LABEL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > select HAVE_BPF_JIT > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..5d24c11 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > index 7ffe03f..ef5b2bb 100644 > --- a/include/linux/bitrev.h > +++ b/include/linux/bitrev.h > @@ -3,6 +3,14 @@ > > #include > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > +#include > + > +#define bitrev32 __arch_bitrev32 > +#define bitrev16 __arch_bitrev16 > +#define bitrev8 __arch_bitrev8 > + > +#else > extern u8 const byte_rev_table[256]; If this is done, the direct uses of byte_rev_table in drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c should be converted too? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Mon, 27 Oct 2014 15:13:50 +0800 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18258@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > > If this is done, the direct uses of byte_rev_table in > drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c > should be converted too? > I think use bitrev8() is safer than to use byte_rev_table[] directly. From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Mon, 27 Oct 2014 10:48:48 +0000 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> Message-ID: <20141027104848.GD8768@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Oct 27, 2014 at 08:02:08AM +0000, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 78 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..c21a5f4 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > + } > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64-bit register. Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Tue, 28 Oct 2014 09:34:42 +0800 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <20141027104848.GD8768@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Will Deacon [mailto:will.deacon at arm.com] > > +++ b/arch/arm/include/asm/bitrev.h > > @@ -0,0 +1,28 @@ > > +#ifndef __ASM_ARM_BITREV_H > > +#define __ASM_ARM_BITREV_H > > + > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x = (x >> 16) | (x << 16); > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > + } > > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64- > bit register. For arm64 in arch/arm64/include/asm/bitrev.h. I have use __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); For arm , I use __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); Am I right ? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Tue, 28 Oct 2014 13:59:44 +0000 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> Message-ID: <20141028135944.GC29706@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Oct 28, 2014 at 01:34:42AM +0000, Wang, Yalin wrote: > > From: Will Deacon [mailto:will.deacon at arm.com] > > > +++ b/arch/arm/include/asm/bitrev.h > > > @@ -0,0 +1,28 @@ > > > +#ifndef __ASM_ARM_BITREV_H > > > +#define __ASM_ARM_BITREV_H > > > + > > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > > +{ > > > + if (__builtin_constant_p(x)) { > > > + x = (x >> 16) | (x << 16); > > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > + } > > > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > > > > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64- > > bit register. > For arm64 in arch/arm64/include/asm/bitrev.h. > I have use __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > For arm , I use __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > Am I right ? Yup, sorry, I didn't realise this patch covered both architectures. It would probably be a good idea to split it into 3 parts: a core part, then the two architectural bits. Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Tue, 28 Oct 2014 14:18:58 -0700 Subject: [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Message-ID: <1414531138.10912.12.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; drivers/net/wireless/ath/carl9170/phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c index b80b213..dca6df1 100644 --- a/drivers/net/wireless/ath/carl9170/phy.c +++ b/drivers/net/wireless/ath/carl9170/phy.c @@ -994,7 +994,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, refsel0 = 0; refsel1 = 1; } - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } else { if (freq == 2484) { chansel = 10 + (freq - 2274) / 5; @@ -1002,7 +1002,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, } else chansel = 16 + (freq - 2272) / 5; chansel *= 4; - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } d1 = chansel; From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Tue, 28 Oct 2014 14:22:49 -0700 Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Message-ID: <1414531369.10912.14.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; sound/usb/6fire/firmware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c index 3b02e54..62c25e7 100644 --- a/sound/usb/6fire/firmware.c +++ b/sound/usb/6fire/firmware.c @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( while (c != end) { for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++) - buffer[i] = byte_rev_table[(u8) *c]; + buffer[i] = bitrev8((u8)*c); ret = usb6fire_fw_fpga_write(device, buffer, i); if (ret < 0) { From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Wed, 29 Oct 2014 10:52:08 +0800 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <20141028135944.GC29706@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> <20141028135944.GC29706@arm.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825D@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Will Deacon [mailto:will.deacon at arm.com] > Yup, sorry, I didn't realise this patch covered both architectures. It > would probably be a good idea to split it into 3 parts: a core part, then > the two architectural bits. > > Will Ok , I will split the patch into three parts, And send again . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Wed, 29 Oct 2014 10:42:00 +0800 Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 In-Reply-To: <1414531369.10912.14.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > to eliminate the array. > > Signed-off-by: Joe Perches > --- > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > hardware. > [] > > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index > > > 7ffe03f..ef5b2bb 100644 > > > --- a/include/linux/bitrev.h > > > +++ b/include/linux/bitrev.h > > > @@ -3,6 +3,14 @@ > > > > > > #include > > > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > > +#include > > > + > > > +#define bitrev32 __arch_bitrev32 > > > +#define bitrev16 __arch_bitrev16 > > > +#define bitrev8 __arch_bitrev8 > > > + > > > +#else > > > extern u8 const byte_rev_table[256]; > > sound/usb/6fire/firmware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c index > 3b02e54..62c25e7 100644 > --- a/sound/usb/6fire/firmware.c > +++ b/sound/usb/6fire/firmware.c > @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( > > while (c != end) { > for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++) > - buffer[i] = byte_rev_table[(u8) *c]; > + buffer[i] = bitrev8((u8)*c); > > ret = usb6fire_fw_fpga_write(device, buffer, i); > if (ret < 0) { > I think the most safe way is change byte_rev_table[] to be satic, So that no driver can access it directly, The build error can remind the developer if they use byte_rev_table[] Directly . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Tue, 28 Oct 2014 20:06:14 -0700 Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> Message-ID: <1414551974.10912.16.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 2014-10-29 at 10:42 +0800, Wang, Yalin wrote: > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > > to eliminate the array. [] > > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > > hardware. [] > I think the most safe way is change byte_rev_table[] to be satic, > So that no driver can access it directly, > The build error can remind the developer if they use byte_rev_table[] > Directly . You can do that with your later patch, but the existing uses _must_ be converted first so you don't break the build. From mboxrd@z Thu Jan 1 00:00:00 1970 From: robherring2@gmail.com (Rob Herring) Date: Wed, 29 Oct 2014 11:28:04 +0800 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Oct 27, 2014 at 2:46 PM, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: >> this change add CONFIG_HAVE_ARCH_BITREVERSE config option, >> so that we can use arm/arm64 rbit instruction to do bitrev operation >> by hardware. I don't see the original patch in my inbox, so replying here. >> >> Signed-off-by: Yalin Wang >> --- >> arch/arm/Kconfig | 1 + >> arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> include/linux/bitrev.h | 9 +++++++++ >> lib/Kconfig | 9 +++++++++ >> lib/bitrev.c | 2 ++ >> 7 files changed, 64 insertions(+) >> create mode 100644 arch/arm/include/asm/bitrev.h >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index 89c4b5c..426cbcc 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -16,6 +16,7 @@ config ARM >> select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS >> select GENERIC_ALLOCATOR >> select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) >> + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) >> select GENERIC_CLOCKEVENTS_BROADCAST if SMP >> select GENERIC_IDLE_POLL_SETUP >> select GENERIC_IRQ_PROBE [...] >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..263c28c 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -36,6 +36,7 @@ config ARM64 >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> select HAVE_ARCH_JUMP_LABEL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> select HAVE_BPF_JIT The kconfig lists should be sorted. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Wed, 29 Oct 2014 11:10:08 +0800 Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 In-Reply-To: <1414551974.10912.16.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> <1414551974.10912.16.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825E@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Joe Perches [mailto:joe at perches.com] > > I think the most safe way is change byte_rev_table[] to be satic, So > > that no driver can access it directly, The build error can remind the > > developer if they use byte_rev_table[] Directly . > > You can do that with your later patch, but the existing uses _must_ be > converted first so you don't break the build. > > Yeah, I agree with you, I will add this into my later patch. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Wed, 29 Oct 2014 13:20:14 +0800 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18262@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Rob Herring [mailto:robherring2 at gmail.com] > >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index > >> 9532f8d..263c28c 100644 > >> --- a/arch/arm64/Kconfig > >> +++ b/arch/arm64/Kconfig > >> @@ -36,6 +36,7 @@ config ARM64 > >> select HARDIRQS_SW_RESEND > >> select HAVE_ARCH_AUDITSYSCALL > >> select HAVE_ARCH_JUMP_LABEL > >> + select HAVE_ARCH_BITREVERSE > >> select HAVE_ARCH_KGDB > >> select HAVE_ARCH_TRACEHOOK > >> select HAVE_BPF_JIT > > The kconfig lists should be sorted. > > Rob Got it , Thanks for your remind. From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Tue, 28 Oct 2014 22:21:36 -0700 Subject: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> Message-ID: <1414560096.10912.18.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, 2014-10-29 at 13:14 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > We also change byte_rev_table[] to be static, > to make sure no drivers can access it directly. You break the build with this patch. You can't do this until the users of the table are converted. So far, they are not. I submitted patches for these uses, but those patches are not yet applied. Please make sure the dependencies for your patches are explicitly stated. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Wed, 29 Oct 2014 13:36:30 +0800 Subject: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <1414560096.10912.18.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <1414560096.10912.18.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18263@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Joe Perches [mailto:joe at perches.com] > > We also change byte_rev_table[] to be static, to make sure no drivers > > can access it directly. > > You break the build with this patch. > > You can't do this until the users of the table are converted. > > So far, they are not. > > I submitted patches for these uses, but those patches are not yet applied. > > Please make sure the dependencies for your patches are explicitly stated. > Oh, byte_rev_table[] must be extern, Otherwise, bitrev8() can't access it , I will change it. From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Thu, 30 Oct 2014 12:01:27 +0000 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> Message-ID: <20141030120127.GC32589@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > 2 files changed, 29 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..292a5de > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); Shouldn't this part be in the generic code? > + } > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); You can write this more neatly as: asm ("rbit %w0, %w0" : "+r" (x)); Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: ard.biesheuvel@linaro.org (Ard Biesheuvel) Date: Thu, 30 Oct 2014 13:26:42 +0100 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 30 October 2014 13:01, Will Deacon wrote: > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: >> This patch add bitrev.h file to support rbit instruction, >> so that we can do bitrev operation by hardware. >> Signed-off-by: Yalin Wang >> --- >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 29 insertions(+) >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..b1ec1dd 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -35,6 +35,7 @@ config ARM64 >> select HANDLE_DOMAIN_IRQ >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_JUMP_LABEL >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h >> new file mode 100644 >> index 0000000..292a5de >> --- /dev/null >> +++ b/arch/arm64/include/asm/bitrev.h >> @@ -0,0 +1,28 @@ >> +#ifndef __ASM_ARM64_BITREV_H >> +#define __ASM_ARM64_BITREV_H >> + >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) >> +{ >> + if (__builtin_constant_p(x)) { >> + x = (x >> 16) | (x << 16); >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > Shouldn't this part be in the generic code? > >> + } >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > You can write this more neatly as: > > asm ("rbit %w0, %w0" : "+r" (x)); > This forces GCC to use the same register as input and output, which doesn't necessarily result in the fastest code. (e.g., if the un-bitrev()'ed value is reused again afterwards). On the other hand, the original notation does allow GCC to use the same register, but doesn't force it to, so I prefer the original one. -- Ard. From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Thu, 30 Oct 2014 13:57:49 +0000 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> Message-ID: <20141030135749.GE32589@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Oct 30, 2014 at 12:26:42PM +0000, Ard Biesheuvel wrote: > On 30 October 2014 13:01, Will Deacon wrote: > > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > >> This patch add bitrev.h file to support rbit instruction, > >> so that we can do bitrev operation by hardware. > >> Signed-off-by: Yalin Wang > >> --- > >> arch/arm64/Kconfig | 1 + > >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > >> 2 files changed, 29 insertions(+) > >> create mode 100644 arch/arm64/include/asm/bitrev.h > >> > >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > >> index 9532f8d..b1ec1dd 100644 > >> --- a/arch/arm64/Kconfig > >> +++ b/arch/arm64/Kconfig > >> @@ -35,6 +35,7 @@ config ARM64 > >> select HANDLE_DOMAIN_IRQ > >> select HARDIRQS_SW_RESEND > >> select HAVE_ARCH_AUDITSYSCALL > >> + select HAVE_ARCH_BITREVERSE > >> select HAVE_ARCH_JUMP_LABEL > >> select HAVE_ARCH_KGDB > >> select HAVE_ARCH_TRACEHOOK > >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > >> new file mode 100644 > >> index 0000000..292a5de > >> --- /dev/null > >> +++ b/arch/arm64/include/asm/bitrev.h > >> @@ -0,0 +1,28 @@ > >> +#ifndef __ASM_ARM64_BITREV_H > >> +#define __ASM_ARM64_BITREV_H > >> + > >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > >> +{ > >> + if (__builtin_constant_p(x)) { > >> + x = (x >> 16) | (x << 16); > >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > > Shouldn't this part be in the generic code? > > > >> + } > >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > > > You can write this more neatly as: > > > > asm ("rbit %w0, %w0" : "+r" (x)); > > > > This forces GCC to use the same register as input and output, which > doesn't necessarily result in the fastest code. (e.g., if the > un-bitrev()'ed value is reused again afterwards). > On the other hand, the original notation does allow GCC to use the > same register, but doesn't force it to, so I prefer the original one. That's a good point, especially since this is __always_inline. Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 31 Oct 2014 10:03:27 +0800 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1826F@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Will Deacon [mailto:will.deacon at arm.com] > Sent: Thursday, October 30, 2014 8:01 PM > To: Wang, Yalin > Cc: 'Rob Herring'; 'Joe Perches'; 'Russell King - ARM Linux'; 'linux- > kernel at vger.kernel.org'; 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; > 'linux-arm-kernel at lists.infradead.org' > Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit > instruction > > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x = (x >> 16) | (x << 16); > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > Shouldn't this part be in the generic code? Good idea, I will change this part into linux/bitrev.h . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Fri, 31 Oct 2014 00:45:35 -0700 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> Message-ID: <1414741535.8928.2.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2014-10-31 at 15:40 +0800, Wang, Yalin wrote: > This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), > because uprobe_notify_resume() have do this. [] > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c [] > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) > return restart; > } > syscall = 0; > - } else if (thread_flags & _TIF_UPROBE) { > - clear_thread_flag(TIF_UPROBE); > + } else if (thread_flags & _TIF_UPROBE) > uprobe_notify_resume(regs); > - } else { > + else { > clear_thread_flag(TIF_NOTIFY_RESUME); > tracehook_notify_resume(regs); > } Please keep the braces. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 31 Oct 2014 15:51:41 +0800 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) In-Reply-To: <1414741535.8928.2.camel@perches.com> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Joe Perches [mailto:joe at perches.com] > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > [] > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > thread_flags, int syscall) > > return restart; > > } > > syscall = 0; > > - } else if (thread_flags & _TIF_UPROBE) { > > - clear_thread_flag(TIF_UPROBE); > > + } else if (thread_flags & _TIF_UPROBE) > > uprobe_notify_resume(regs); > > - } else { > > + else { > > clear_thread_flag(TIF_NOTIFY_RESUME); > > tracehook_notify_resume(regs); > > } > > Please keep the braces. mm.. could I know the reason ? :) Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 31 Oct 2014 15:54:16 +0800 Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827D@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Wang, Yalin > Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit > instruction > > This patch add bitrev.h file to support rbit instruction, so that we can do > bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b > 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git > a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file > mode 100644 index 0000000..e9b2571 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) { > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) { > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) { > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > -- > 2.1.1 Wrong title, please ignore this one , I have resend another [RFC V6 2/3] . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Fri, 31 Oct 2014 00:58:09 -0700 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> Message-ID: <1414742289.8928.5.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2014-10-31 at 15:51 +0800, Wang, Yalin wrote: > > From: Joe Perches [mailto:joe at perches.com] > > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > > [] > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > > thread_flags, int syscall) > > > return restart; > > > } > > > syscall = 0; > > > - } else if (thread_flags & _TIF_UPROBE) { > > > - clear_thread_flag(TIF_UPROBE); > > > + } else if (thread_flags & _TIF_UPROBE) > > > uprobe_notify_resume(regs); > > > - } else { > > > + else { > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > tracehook_notify_resume(regs); > > > } > > > > Please keep the braces. > > mm.. could I know the reason ? :) Try read Documentation/CodingStyle Chapter 3: Placing Braces and Spaces use braces in both branches: if (condition) { do_this(); do_that(); } else { otherwise(); } From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 31 Oct 2014 15:59:37 +0800 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) In-Reply-To: <1414742289.8928.5.camel@perches.com> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> <1414742289.8928.5.camel@perches.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827E@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Joe Perches [mailto:joe at perches.com] > > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned > int > > > thread_flags, int syscall) > > > > return restart; > > > > } > > > > syscall = 0; > > > > - } else if (thread_flags & _TIF_UPROBE) { > > > > - clear_thread_flag(TIF_UPROBE); > > > > + } else if (thread_flags & _TIF_UPROBE) > > > > uprobe_notify_resume(regs); > > > > - } else { > > > > + else { > > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > > tracehook_notify_resume(regs); > > > > } > > > > > > Please keep the braces. > > > > mm.. could I know the reason ? :) > > Try read Documentation/CodingStyle > > Chapter 3: Placing Braces and Spaces > > use braces in both branches: > > if (condition) { > do_this(); > do_that(); > } else { > otherwise(); > } > Got it, I will resend one . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Fri, 31 Oct 2014 10:43:06 +0000 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> Message-ID: <20141031104305.GC6731@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Oct 31, 2014 at 05:41:48AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..706a209 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H Really minor nit, but we don't tend to include 'ARM64' in our header guards, so this should just be __ASM_BITREV_H. With that change, Acked-by: Will Deacon Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Mon, 3 Nov 2014 10:17:15 +0800 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <20141031104305.GC6731@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Will Deacon [mailto:will.deacon at arm.com] > > +#ifndef __ASM_ARM64_BITREV_H > > +#define __ASM_ARM64_BITREV_H > > Really minor nit, but we don't tend to include 'ARM64' in our header guards, > so this should just be __ASM_BITREV_H. > > With that change, > > Acked-by: Will Deacon > I have send the patch to the patch system: http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 8187/1 8188/1 8189/1 Just remind you that , should also cherry-pick Joe Perches's 2 patches: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 To make sure there is no build error when build these 2 drivers. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: ard.biesheuvel@linaro.org (Ard Biesheuvel) Date: Mon, 3 Nov 2014 09:47:32 +0100 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 3 November 2014 03:17, Wang, Yalin wrote: >> From: Will Deacon [mailto:will.deacon at arm.com] >> > +#ifndef __ASM_ARM64_BITREV_H >> > +#define __ASM_ARM64_BITREV_H >> >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, >> so this should just be __ASM_BITREV_H. >> >> With that change, >> >> Acked-by: Will Deacon >> > I have send the patch to the patch system: > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > 8187/1 8188/1 8189/1 > > Just remind you that , should also cherry-pick Joe Perches's > 2 patches: > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > To make sure there is no build error when build these 2 drivers. > If this is the case, I suggest you update patch 8187/1 to retain the byte_rev_table symbol, even in the accelerated case, and remove it with a followup patch once Joe's patches have landed upstream. Also, a link to the patches would be nice, and perhaps a bit of explanation how/when they are expected to be merged. -- Ard. From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Mon, 3 Nov 2014 09:50:51 +0000 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> Message-ID: <20141103095051.GA23019@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 03, 2014 at 08:47:32AM +0000, Ard Biesheuvel wrote: > On 3 November 2014 03:17, Wang, Yalin wrote: > >> From: Will Deacon [mailto:will.deacon at arm.com] > >> > +#ifndef __ASM_ARM64_BITREV_H > >> > +#define __ASM_ARM64_BITREV_H > >> > >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, > >> so this should just be __ASM_BITREV_H. > >> > >> With that change, > >> > >> Acked-by: Will Deacon > >> > > I have send the patch to the patch system: > > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > > > 8187/1 8188/1 8189/1 > > > > Just remind you that , should also cherry-pick Joe Perches's > > 2 patches: > > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > > > To make sure there is no build error when build these 2 drivers. > > > > If this is the case, I suggest you update patch 8187/1 to retain the > byte_rev_table symbol, even in the accelerated case, and remove it > with a followup patch once Joe's patches have landed upstream. Also, a > link to the patches would be nice, and perhaps a bit of explanation > how/when they are expected to be merged. Indeed, or instead put together a series with the appropriate acks so somebody can merge it all in one go. Merging this on a piecemeal basis is going to cause breakages (as you pointed out). Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Tue, 4 Nov 2014 09:45:42 +0800 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction In-Reply-To: <20141103095051.GA23019@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> <20141103095051.GA23019@arm.com> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18288@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Will Deacon [mailto:will.deacon at arm.com] > > > > If this is the case, I suggest you update patch 8187/1 to retain the > > byte_rev_table symbol, even in the accelerated case, and remove it > > with a followup patch once Joe's patches have landed upstream. Also, a > > link to the patches would be nice, and perhaps a bit of explanation > > how/when they are expected to be merged. > > Indeed, or instead put together a series with the appropriate acks so > somebody can merge it all in one go. Merging this on a piecemeal basis is > going to cause breakages (as you pointed out). > > Will Hi Will, Could I add you as ack-by , and submit these 2 patches into the Patch system ? So you can merge them together . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Thu, 13 Nov 2014 23:53:22 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> Message-ID: <20141113235322.GC4042@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..be92b3b 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) Looking at this, this is just wrong. Take a moment to consider what happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. What happens if an ARMv6 CPU tries to execute an rbit instruction? Second point (which isn't obvious from your submissions on-list) is that you've loaded the patch system up with patches for other parts of the kernel tree for which I am not responsible for. As such, I can't take those patches without the sub-tree maintainer acking them. Also, the commit text in those patches look weird: 6fire: Convert byte_rev_table uses to bitrev8 Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches <(address hidden)> Signed-off-by: Yalin Wang <(address hidden)> Why is Joe signing off on these patches? As his is the first sign-off, one assumes that he was responsible for creating the patch in the first place, but there is no From: line marking him as the author. Shouldn't his entry be an Acked-by: ? Confused. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Thu, 13 Nov 2014 16:05:30 -0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> Message-ID: <1415923530.4223.17.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, > > so that we can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: > > 6fire: Convert byte_rev_table uses to bitrev8 > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit > reversals to eliminate the array. > > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> > > Why is Joe signing off on these patches? > Shouldn't his entry be an Acked-by: ? I didn't sign off on or ack the "add bitrev.h" patch. I created 2 patches that converted direct uses of byte_rev_table to that bitrev8 static inline. One of them is already in -next 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 The other hasn't been applied. https://lkml.org/lkml/2014/10/28/1056 Maybe Takashi Iwai will get around to it one day. From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 14 Nov 2014 00:17:21 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415923530.4223.17.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> Message-ID: <20141114001720.GD4042@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. Correct, I never said you did. Please read my message a bit more carefully next time, huh? > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. Great, so I can just discard these that were incorrectly submitted to me then. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Thu, 13 Nov 2014 16:45:43 -0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20141114001720.GD4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> Message-ID: <1415925943.4141.1.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > Correct, I never said you did. Please read my message a bit more carefully > next time, huh? You've no reason to write that Russell. I'm not trying to be anything other than clear and no I didn't say you said that either. Why not make your own writing clearer or your own memory sharper then eh? Reply on the patch I actually wrote. You were cc'd on it when I submitted it. > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > Great, so I can just discard these that were incorrectly submitted to me > then. I think you shouldn't apply these patches or updated ones either until all the current uses are converted. cheers, Joe From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 14 Nov 2014 01:18:32 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415925943.4141.1.camel@perches.com> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> Message-ID: <20141114011832.GE4042@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > Correct, I never said you did. Please read my message a bit more carefully > > next time, huh? > > You've no reason to write that Russell. Absolutely I have, but I'm not going to discuss it because I'll just end up flaming you because in my mind you are the one who is completely mistaken with your comments. In case it hasn't been realised, I hardly read this mailing list anymore, or messages that I'm Cc'd on. I do read most messages that I'm in the To: line, but generally not if they're DT changes (which always end up being marked To: me.) > > Great, so I can just discard these that were incorrectly submitted to me > > then. > > I think you shouldn't apply these patches or updated > ones either until all the current uses are converted. Where are the dependencies mentioned? How do I get to know when all the dependencies are met? Who is tracking the dependencies? -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Thu, 13 Nov 2014 17:26:34 -0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20141114011832.GE4042@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> Message-ID: <1415928394.4141.3.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > I think you shouldn't apply these patches or updated > > ones either until all the current uses are converted. > > Where are the dependencies mentioned? I mentioned it when these patches (which are not mine btw), were submitted the second time. https://lkml.org/lkml/2014/10/27/69 > How do I get to know when all > the dependencies are met? No idea. > Who is tracking the dependencies? Not me. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 14 Nov 2014 10:01:34 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, November 14, 2014 7:53 AM > To: Wang, Yalin > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, so that we > > can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? Is it possible to build a kernel that support both CPU_V6 and CPU_V7? I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? If there is problem like you said, How about this solution: select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: > > 6fire: Convert byte_rev_table uses to bitrev8 > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > to eliminate the array. > > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> > > Why is Joe signing off on these patches? As his is the first sign-off, one > assumes that he was responsible for creating the patch in the first place, > but there is no From: line marking him as the author. Shouldn't his entry > be an Acked-by: ? > > Confused. For this patch, I just cherry-pick from Joe, If you are not responsible for this part, I will submit to the maintainers for these patches . Sorry for that . From mboxrd@z Thu Jan 1 00:00:00 1970 From: tiwai@suse.de (Takashi Iwai) Date: Fri, 14 Nov 2014 07:37:13 +0100 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415923530.4223.17.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org At Thu, 13 Nov 2014 16:05:30 -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. > > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. It was not clear to me whether I should apply it individually from others in the whole thread. Your description looked as if it makes sense only with ARM's bitrev8 support. So, again: should I apply this now to my tree? Takashi From mboxrd@z Thu Jan 1 00:00:00 1970 From: joe@perches.com (Joe Perches) Date: Thu, 13 Nov 2014 22:55:09 -0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> Message-ID: <1415948109.5912.12.camel@perches.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > At Thu, 13 Nov 2014 16:05:30 -0800, > Joe Perches wrote: > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > It was not clear to me whether I should apply it individually from > others in the whole thread. Your description looked as if it makes > sense only with ARM's bitrev8 support. > > So, again: should I apply this now to my tree? I it would be good to apply even if the bitrev patch for arm is never applied. $ git grep -w bitrev8 | wc -l 110 vs this last direct use of byte_rev_table. cheers, Joe From mboxrd@z Thu Jan 1 00:00:00 1970 From: tiwai@suse.de (Takashi Iwai) Date: Fri, 14 Nov 2014 08:03:01 +0100 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415948109.5912.12.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <1415948109.5912.12.camel@perches.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org At Thu, 13 Nov 2014 22:55:09 -0800, Joe Perches wrote: > > On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > > At Thu, 13 Nov 2014 16:05:30 -0800, > > Joe Perches wrote: > > > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > > > I created 2 patches that converted direct uses of byte_rev_table > > > to that bitrev8 static inline. One of them is already in -next > > > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > > > The other hasn't been applied. > > > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > > > Maybe Takashi Iwai will get around to it one day. > > > > It was not clear to me whether I should apply it individually from > > others in the whole thread. Your description looked as if it makes > > sense only with ARM's bitrev8 support. > > > > So, again: should I apply this now to my tree? > > I it would be good to apply even if the > bitrev patch for arm is never applied. > > $ git grep -w bitrev8 | wc -l > 110 > > vs > > this last direct use of byte_rev_table. Alright, I picked up your original patch and merged. thanks, Takashi From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 14 Nov 2014 09:52:06 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415928394.4141.3.camel@perches.com> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> <1415928394.4141.3.camel@perches.com> Message-ID: <20141114095205.GF4042@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Nov 13, 2014 at 05:26:34PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > > I think you shouldn't apply these patches or updated > > > ones either until all the current uses are converted. > > > > Where are the dependencies mentioned? > > I mentioned it when these patches (which are not > mine btw), were submitted the second time. Yes, I'm well aware that the author of the ARM patches are Yalin Wang. > https://lkml.org/lkml/2014/10/27/69 > > > How do I get to know when all > > the dependencies are met? > > No idea. > > > Who is tracking the dependencies? > > Not me. Right, what that means is that no one is doing that. What you've also said in this thread now is that the ARM patches should not be applied until all the other users are converted. As those patches are going via other trees, that means the ARM patches can only be applied _after_ the next merge window _if_ all maintainers pick up the previous set. As I'm not tracking the status of what other maintainers do, I'm simply going to avoid applying these patches until after the next merge window and hope that the other maintainers pick the dependent patches up and get them in during the next merge window. If not, I guess we'll see compile breakage. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 14 Nov 2014 09:58:12 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> Message-ID: <20141114095812.GG4042@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Nov 14, 2014 at 10:01:34AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > > Sent: Friday, November 14, 2014 7:53 AM > > To: Wang, Yalin > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, so that we > > > can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > > 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? Absolutely it is. > I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? Yes. > If there is problem like you said, > How about this solution: > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) That would work. > For this patch, > I just cherry-pick from Joe, > If you are not responsible for this part, > I will submit to the maintainers for these patches . > Sorry for that . I think you need to discuss with Joe how Joe would like his patches handled. However, it seems that Joe already sent his patches to the appropriate maintainers, and they have been applying those patches themselves. Since your generic ARM changes depend on these patches being accepted first, this means is that I can't apply the generic ARM changes until those other patches have hit mainline, otherwise things are going to break. So, when you come to submit the latest set of patches to the patch system, please do so only after these dependent patches have been merged into mainline so that they don't get accidentally applied before hand and break the two drivers that Joe mentioned. Thanks. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Mon, 17 Nov 2014 10:38:58 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20141114095812.GG4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> Message-ID: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, November 14, 2014 5:58 PM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel at vger.kernel.org'; > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; 'linux-arm- > kernel at lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? > > Absolutely it is. > > > I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? > > Yes. > > > If there is problem like you said, > > How about this solution: > > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > That would work. > OK, I will submit a patch for this change. > > For this patch, > > I just cherry-pick from Joe, > > If you are not responsible for this part, I will submit to the > > maintainers for these patches . > > Sorry for that . > > I think you need to discuss with Joe how Joe would like his patches handled. > However, it seems that Joe already sent his patches to the appropriate > maintainers, and they have been applying those patches themselves. > > Since your generic ARM changes depend on these patches being accepted first, > this means is that I can't apply the generic ARM changes until those other > patches have hit mainline, otherwise things are going to break. So, when > you come to submit the latest set of patches to the patch system, please do > so only after these dependent patches have been merged into mainline so > that they don't get accidentally applied before hand and break the two > drivers that Joe mentioned. Joe has submitted patches to maintainers, So we need wait for them to be accepted . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Thu, 8 Jan 2015 18:40:59 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> Message-ID: <20150108184059.GZ12302@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > Joe has submitted patches to maintainers, > So we need wait for them to be accepted . I ran these patches through my autobuilder, and while most builds didn't seem to be a problem, the randconfigs found errors: /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode `rbit r3,r2' /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode `rbit r0,r1' make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode `rbit r2,r2' make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode `rbit r2,r2' /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode `rbit r1,r1' /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode `rbit r3,r3' /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode `rbit r5,r5' /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 The root cause is that the kernel being built is supposed to support both ARMv7 and ARMv6K CPUs. However, "rbit" is only available on ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 9 Jan 2015 10:16:32 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20150108184059.GZ12302@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, January 09, 2015 2:41 AM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel at vger.kernel.org'; > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; 'linux-arm- > kernel at lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > > Joe has submitted patches to maintainers, So we need wait for them to > > be accepted . > > I ran these patches through my autobuilder, and while most builds didn't > seem to be a problem, the randconfigs found errors: > > /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode > `rbit r3,r2' > /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode > `rbit r0,r1' > make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 > > /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode > `rbit r2,r2' > make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 > > /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode > `rbit r2,r2' > /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 > > /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode > `rbit r1,r1' > /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode > `rbit r3,r3' > /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode > `rbit r5,r5' > /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 > > The root cause is that the kernel being built is supposed to support both > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > In the patch that you applied: 8205/1 add bitrev.h file to support rbit instruction I have add : + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? Then will not build hardware rbit instruction, isn't it ? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 9 Jan 2015 11:10:48 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> Message-ID: <20150109111048.GE12302@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > > Sent: Friday, January 09, 2015 2:41 AM > > To: Wang, Yalin > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel at vger.kernel.org'; > > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; 'linux-arm- > > kernel at lists.infradead.org' > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > > > The root cause is that the kernel being built is supposed to support both > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > In the patch that you applied: > 8205/1 add bitrev.h file to support rbit instruction > > I have add : > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? > Then will not build hardware rbit instruction, isn't it ? The config has: CONFIG_CPU_PJ4=y # CONFIG_CPU_V6 is not set CONFIG_CPU_V6K=y CONFIG_CPU_V7=y CONFIG_CPU_32v6=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y And no, the CONFIG_CPU_V* flags refer to the CPUs. The CONFIG_CPU_32v* symbols refer to the CPU architectures. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 9 Jan 2015 20:40:56 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20150109111048.GE12302@n2100.arm.linux.org.uk> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Friday, January 09, 2015 7:11 PM > To: Wang, Yalin > Cc: 'Ard Biesheuvel'; 'Will Deacon'; 'linux-kernel at vger.kernel.org'; > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; 'linux-arm- > kernel at lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > > -----Original Message----- > > > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > > > Sent: Friday, January 09, 2015 2:41 AM > > > To: Wang, Yalin > > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel at vger.kernel.org'; > > > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; > > > 'linux-arm- kernel at lists.infradead.org' > > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit > > > instruction > > > > > > The root cause is that the kernel being built is supposed to support > > > both > > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > > > In the patch that you applied: > > 8205/1 add bitrev.h file to support rbit instruction > > > > I have add : > > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? > > Then will not build hardware rbit instruction, isn't it ? > > The config has: > > CONFIG_CPU_PJ4=y > # CONFIG_CPU_V6 is not set > CONFIG_CPU_V6K=y > CONFIG_CPU_V7=y > CONFIG_CPU_32v6=y > CONFIG_CPU_32v6K=y > CONFIG_CPU_32v7=y > > And no, the CONFIG_CPU_V* flags refer to the CPUs. The > CONFIG_CPU_32v* symbols refer to the CPU architectures. > Oh, I see, How about change like this: + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6K) I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&?!CPU_ARM940T ? Another solution is: + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) By the way, I am not clear about the difference between CPU_V6 and CPU_V6K, could you tell me? :) Thank you From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Wed, 14 Jan 2015 16:38:00 +0000 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> Message-ID: <20150114163800.GZ12302@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 09, 2015 at 08:40:56PM +0800, Wang, Yalin wrote: > Oh, I see, > How about change like this: > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6K) > I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&?!CPU_ARM940T ? > > Another solution is: > + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) > > By the way, I am not clear about the difference between CPU_V6 and CPU_V6K, could you tell me? :) I think select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 is sufficient - we don't support mixing pre-v6 and v6+ CPU architectures into a single kernel. -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yalin.Wang@sonymobile.com (Wang, Yalin) Date: Fri, 16 Jan 2015 09:42:23 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <20150114163800.GZ12302@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> <20150114163800.GZ12302@n2100.arm.linux.org.uk> Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E1B0@CNBJMBX05.corpusers.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] > Sent: Thursday, January 15, 2015 12:38 AM > To: Wang, Yalin > Cc: 'Ard Biesheuvel'; 'Will Deacon'; 'linux-kernel at vger.kernel.org'; > 'akinobu.mita at gmail.com'; 'linux-mm at kvack.org'; 'Joe Perches'; 'linux-arm- > kernel at lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Fri, Jan 09, 2015 at 08:40:56PM +0800, Wang, Yalin wrote: > > Oh, I see, > > How about change like this: > > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && > > +!CPU_V6K) > > I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI > &&?!CPU_ARM940T ? > > > > Another solution is: > > + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 > > +&& !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) > > > > By the way, I am not clear about the difference between CPU_V6 and > > CPU_V6K, could you tell me? :) > > I think > > select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 > > is sufficient - we don't support mixing pre-v6 and v6+ CPU architectures > into a single kernel. > Ok, I will re-send a patch. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f48.google.com (mail-pa0-f48.google.com [209.85.220.48]) by kanga.kvack.org (Postfix) with ESMTP id C95D282BDA for ; Fri, 24 Oct 2014 01:10:42 -0400 (EDT) Received: by mail-pa0-f48.google.com with SMTP id ey11so471031pad.7 for ; Thu, 23 Oct 2014 22:10:42 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id z3si3282750pas.143.2014.10.23.22.10.40 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 23 Oct 2014 22:10:41 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 24 Oct 2014 13:10:33 +0800 Subject: [PATCH RFC] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 8 ++++++++ lib/bitrev.c | 2 ++ 7 files changed, 63 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..0df5866 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index ac9afde..a2566d7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitre= v.h new file mode 100644 index 0000000..5d24c11 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ =20 #include =20 +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; =20 static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); =20 +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..e0e0453 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,14 @@ config RAID6_PQ config BITREVERSE tristate =20 +config HAVE_ARCH_BITREVERSE + boolean + default n + help + This option provides an config for the architecture which have instruct= ion + can do bitreverse operation, we use the hardware instruction if the arc= hitecture + have this capability. + config RATIONAL boolean =20 diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f179.google.com (mail-pd0-f179.google.com [209.85.192.179]) by kanga.kvack.org (Postfix) with ESMTP id 834056B0069 for ; Mon, 27 Oct 2014 02:38:54 -0400 (EDT) Received: by mail-pd0-f179.google.com with SMTP id g10so5069726pdj.10 for ; Sun, 26 Oct 2014 23:38:54 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id uh7si9722857pac.156.2014.10.26.23.38.45 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 26 Oct 2014 23:38:53 -0700 (PDT) From: "Wang, Yalin" Date: Mon, 27 Oct 2014 14:37:28 +0800 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 9 +++++++++ lib/bitrev.c | 2 ++ 7 files changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..0df5866 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..263c28c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -36,6 +36,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitre= v.h new file mode 100644 index 0000000..5d24c11 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ =20 #include =20 +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; =20 static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); =20 +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate =20 +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruct= ion + can do bitreverse operation, we use the hardware instruction if the arc= hitecture + have this capability. + config RATIONAL boolean =20 diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f169.google.com (mail-ig0-f169.google.com [209.85.213.169]) by kanga.kvack.org (Postfix) with ESMTP id EE8FC6B006C for ; Mon, 27 Oct 2014 02:46:14 -0400 (EDT) Received: by mail-ig0-f169.google.com with SMTP id uq10so5347922igb.0 for ; Sun, 26 Oct 2014 23:46:14 -0700 (PDT) Received: from smtprelay.hostedemail.com (smtprelay0021.hostedemail.com. [216.40.44.21]) by mx.google.com with ESMTP id zc3si15571006icb.50.2014.10.26.23.46.14 for ; Sun, 26 Oct 2014 23:46:14 -0700 (PDT) Message-ID: <1414392371.8884.2.camel@perches.com> Subject: Re: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction From: Joe Perches Date: Sun, 26 Oct 2014 23:46:11 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 64 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..0df5866 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..263c28c 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -36,6 +36,7 @@ config ARM64 > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > select HAVE_ARCH_JUMP_LABEL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > select HAVE_BPF_JIT > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..5d24c11 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > index 7ffe03f..ef5b2bb 100644 > --- a/include/linux/bitrev.h > +++ b/include/linux/bitrev.h > @@ -3,6 +3,14 @@ > > #include > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > +#include > + > +#define bitrev32 __arch_bitrev32 > +#define bitrev16 __arch_bitrev16 > +#define bitrev8 __arch_bitrev8 > + > +#else > extern u8 const byte_rev_table[256]; If this is done, the direct uses of byte_rev_table in drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c should be converted too? -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f182.google.com (mail-pd0-f182.google.com [209.85.192.182]) by kanga.kvack.org (Postfix) with ESMTP id A52D26B006E for ; Mon, 27 Oct 2014 03:13:59 -0400 (EDT) Received: by mail-pd0-f182.google.com with SMTP id fp1so1841541pdb.13 for ; Mon, 27 Oct 2014 00:13:59 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id nr9si9785010pbc.113.2014.10.27.00.13.56 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 27 Oct 2014 00:13:58 -0700 (PDT) From: "Wang, Yalin" Date: Mon, 27 Oct 2014 15:13:50 +0800 Subject: RE: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18258@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: <1414392371.8884.2.camel@perches.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Joe Perches' Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" >=20 > If this is done, the direct uses of byte_rev_table in > drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c > should be converted too? >=20 I think use bitrev8() is safer than to use byte_rev_table[] directly. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f177.google.com (mail-pd0-f177.google.com [209.85.192.177]) by kanga.kvack.org (Postfix) with ESMTP id 54A986B0069 for ; Mon, 27 Oct 2014 04:02:19 -0400 (EDT) Received: by mail-pd0-f177.google.com with SMTP id v10so5110209pde.8 for ; Mon, 27 Oct 2014 01:02:19 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id cq3si9807716pbb.193.2014.10.27.01.02.15 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 27 Oct 2014 01:02:17 -0700 (PDT) From: "Wang, Yalin" Date: Mon, 27 Oct 2014 16:02:08 +0800 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 9 +++++++++ lib/bitrev.c | 2 ++ 7 files changed, 78 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..c21a5f4 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x =3D (x >> 16) | (x << 16); + x =3D ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x =3D ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x =3D ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..263c28c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -36,6 +36,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitre= v.h new file mode 100644 index 0000000..f725a71 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x =3D (x >> 16) | (x << 16); + x =3D ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x =3D ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x =3D ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %w0, %w1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ =20 #include =20 +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; =20 static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); =20 +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate =20 +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruct= ion + can do bitreverse operation, we use the hardware instruction if the arc= hitecture + have this capability. + config RATIONAL boolean =20 diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f172.google.com (mail-pd0-f172.google.com [209.85.192.172]) by kanga.kvack.org (Postfix) with ESMTP id 3743D6B0069 for ; Mon, 27 Oct 2014 06:49:11 -0400 (EDT) Received: by mail-pd0-f172.google.com with SMTP id r10so5418536pdi.17 for ; Mon, 27 Oct 2014 03:49:10 -0700 (PDT) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id se6si10316928pac.1.2014.10.27.03.49.09 for ; Mon, 27 Oct 2014 03:49:10 -0700 (PDT) Date: Mon, 27 Oct 2014 10:48:48 +0000 From: Will Deacon Subject: Re: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <20141027104848.GD8768@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" On Mon, Oct 27, 2014 at 08:02:08AM +0000, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 78 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..c21a5f4 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > + } > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64-bit register. Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f41.google.com (mail-pa0-f41.google.com [209.85.220.41]) by kanga.kvack.org (Postfix) with ESMTP id 0B4A1900021 for ; Mon, 27 Oct 2014 21:35:18 -0400 (EDT) Received: by mail-pa0-f41.google.com with SMTP id rd3so6672410pab.0 for ; Mon, 27 Oct 2014 18:35:18 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id fo9si11737364pdb.175.2014.10.27.18.34.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 27 Oct 2014 18:35:18 -0700 (PDT) From: "Wang, Yalin" Date: Tue, 28 Oct 2014 09:34:42 +0800 Subject: RE: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> In-Reply-To: <20141027104848.GD8768@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" > From: Will Deacon [mailto:will.deacon@arm.com] > > +++ b/arch/arm/include/asm/bitrev.h > > @@ -0,0 +1,28 @@ > > +#ifndef __ASM_ARM_BITREV_H > > +#define __ASM_ARM_BITREV_H > > + > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x =3D (x >> 16) | (x << 16); > > + x =3D ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x =3D ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x =3D ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > + } > > + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); >=20 > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 6= 4- > bit register. For arm64 in arch/arm64/include/asm/bitrev.h. I have use __asm__ ("rbit %w0, %w1" : "=3Dr" (x) : "r" (x)); For arm , I use __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); Am I right ? Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by kanga.kvack.org (Postfix) with ESMTP id C2193900021 for ; Tue, 28 Oct 2014 09:59:56 -0400 (EDT) Received: by mail-pa0-f49.google.com with SMTP id lj1so789308pab.22 for ; Tue, 28 Oct 2014 06:59:56 -0700 (PDT) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id x3si1475177pdm.53.2014.10.28.06.59.55 for ; Tue, 28 Oct 2014 06:59:55 -0700 (PDT) Date: Tue, 28 Oct 2014 13:59:44 +0000 From: Will Deacon Subject: Re: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <20141028135944.GC29706@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" On Tue, Oct 28, 2014 at 01:34:42AM +0000, Wang, Yalin wrote: > > From: Will Deacon [mailto:will.deacon@arm.com] > > > +++ b/arch/arm/include/asm/bitrev.h > > > @@ -0,0 +1,28 @@ > > > +#ifndef __ASM_ARM_BITREV_H > > > +#define __ASM_ARM_BITREV_H > > > + > > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > > +{ > > > + if (__builtin_constant_p(x)) { > > > + x = (x >> 16) | (x << 16); > > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > + } > > > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > > > > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64- > > bit register. > For arm64 in arch/arm64/include/asm/bitrev.h. > I have use __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > For arm , I use __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > Am I right ? Yup, sorry, I didn't realise this patch covered both architectures. It would probably be a good idea to split it into 3 parts: a core part, then the two architectural bits. Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by kanga.kvack.org (Postfix) with ESMTP id 8FB04900021 for ; Tue, 28 Oct 2014 22:52:16 -0400 (EDT) Received: by mail-pa0-f52.google.com with SMTP id fa1so2144793pad.39 for ; Tue, 28 Oct 2014 19:52:16 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id l3si2841288pdc.176.2014.10.28.19.52.14 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 19:52:15 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 10:52:08 +0800 Subject: RE: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825D@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> <20141028135944.GC29706@arm.com> In-Reply-To: <20141028135944.GC29706@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' Cc: 'Russell King - ARM Linux' , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" > From: Will Deacon [mailto:will.deacon@arm.com] > Yup, sorry, I didn't realise this patch covered both architectures. It > would probably be a good idea to split it into 3 parts: a core part, then > the two architectural bits. >=20 > Will Ok , I will split the patch into three parts, And send again . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f180.google.com (mail-ig0-f180.google.com [209.85.213.180]) by kanga.kvack.org (Postfix) with ESMTP id 3C107900021 for ; Tue, 28 Oct 2014 17:19:03 -0400 (EDT) Received: by mail-ig0-f180.google.com with SMTP id h3so1929777igd.1 for ; Tue, 28 Oct 2014 14:19:03 -0700 (PDT) Received: from smtprelay.hostedemail.com (smtprelay0189.hostedemail.com. [216.40.44.189]) by mx.google.com with ESMTP id ds9si4231298icc.92.2014.10.28.14.19.02 for ; Tue, 28 Oct 2014 14:19:02 -0700 (PDT) Message-ID: <1414531138.10912.12.camel@perches.com> Subject: [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 From: Joe Perches Date: Tue, 28 Oct 2014 14:18:58 -0700 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Christian Lamparter Cc: "John W. Linville" , "Wang, Yalin" , Russell King , linux-mm@kvack.org, Will Deacon , Akinobu Mita , linux-arm-kernel@lists.infradead.org, linux-wireless@vger.kernel.org, netdev , LKML Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; drivers/net/wireless/ath/carl9170/phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c index b80b213..dca6df1 100644 --- a/drivers/net/wireless/ath/carl9170/phy.c +++ b/drivers/net/wireless/ath/carl9170/phy.c @@ -994,7 +994,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, refsel0 = 0; refsel1 = 1; } - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } else { if (freq == 2484) { chansel = 10 + (freq - 2274) / 5; @@ -1002,7 +1002,7 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, } else chansel = 16 + (freq - 2272) / 5; chansel *= 4; - chansel = byte_rev_table[chansel]; + chansel = bitrev8(chansel); } d1 = chansel; -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by kanga.kvack.org (Postfix) with ESMTP id C7FB4900021 for ; Wed, 29 Oct 2014 01:14:33 -0400 (EDT) Received: by mail-pa0-f54.google.com with SMTP id rd3so2401642pab.27 for ; Tue, 28 Oct 2014 22:14:33 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id zt1si3203207pac.10.2014.10.28.22.14.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:14:32 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:14:18 +0800 Subject: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , Joe Perches Cc: Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" 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For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f43.google.com (mail-pa0-f43.google.com [209.85.220.43]) by kanga.kvack.org (Postfix) with ESMTP id 88623900021 for ; Tue, 28 Oct 2014 23:16:20 -0400 (EDT) Received: by mail-pa0-f43.google.com with SMTP id eu11so2198695pac.16 for ; Tue, 28 Oct 2014 20:16:20 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id ab8si2989180pbd.32.2014.10.28.20.16.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 20:16:19 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 11:10:08 +0800 Subject: RE: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825E@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> <1414551974.10912.16.camel@perches.com> In-Reply-To: <1414551974.10912.16.camel@perches.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Joe Perches' Cc: Jaroslav Kysela , Takashi Iwai , Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML > From: Joe Perches [mailto:joe@perches.com] > > I think the most safe way is change byte_rev_table[] to be satic, So > > that no driver can access it directly, The build error can remind the > > developer if they use byte_rev_table[] Directly . >=20 > You can do that with your later patch, but the existing uses _must_ be > converted first so you don't break the build. >=20 >=20 Yeah, I agree with you, I will add this into my later patch. Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by kanga.kvack.org (Postfix) with ESMTP id 12201900021 for ; Wed, 29 Oct 2014 01:15:47 -0400 (EDT) Received: by mail-pa0-f49.google.com with SMTP id lj1so2370431pab.36 for ; Tue, 28 Oct 2014 22:15:46 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id kv12si3030558pab.232.2014.10.28.22.15.44 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:15:46 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:15:38 +0800 Subject: [RFC V4 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , 'Joe Perches' Cc: 'Russell King - ARM Linux' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" VGhpcyBwYXRjaCBhZGQgYml0cmV2LmggZmlsZSB0byBzdXBwb3J0IHJiaXQgaW5zdHJ1Y3Rpb24s DQpzbyB0aGF0IHdlIGNhbiBkbyBiaXRyZXYgb3BlcmF0aW9uIGJ5IGhhcmR3YXJlLg0KU2lnbmVk LW9mZi1ieTogWWFsaW4gV2FuZyA8eWFsaW4ud2FuZ0Bzb255bW9iaWxlLmNvbT4NCi0tLQ0KIGFy Y2gvYXJtL0tjb25maWcgICAgICAgICAgICAgIHwgIDEgKw0KIGFyY2gvYXJtL2luY2x1ZGUvYXNt L2JpdHJldi5oIHwgMjggKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KIDIgZmlsZXMgY2hh bmdlZCwgMjkgaW5zZXJ0aW9ucygrKQ0KIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9pbmNs dWRlL2FzbS9iaXRyZXYuaA0KDQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vS2NvbmZpZyBiL2FyY2gv YXJtL0tjb25maWcNCmluZGV4IDg5YzRiNWMuLmJlOTJiM2IgMTAwNjQ0DQotLS0gYS9hcmNoL2Fy bS9LY29uZmlnDQorKysgYi9hcmNoL2FybS9LY29uZmlnDQpAQCAtMjgsNiArMjgsNyBAQCBjb25m aWcgQVJNDQogCXNlbGVjdCBIQU5ETEVfRE9NQUlOX0lSUQ0KIAlzZWxlY3QgSEFSRElSUVNfU1df UkVTRU5EDQogCXNlbGVjdCBIQVZFX0FSQ0hfQVVESVRTWVNDQUxMIGlmIChBRUFCSSAmJiAhT0FC SV9DT01QQVQpDQorCXNlbGVjdCBIQVZFX0FSQ0hfQklUUkVWRVJTRSBpZiAoQ1BVX1Y3TSB8fCBD UFVfVjcpDQogCXNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTCBpZiAhWElQX0tFUk5FTA0KIAlz ZWxlY3QgSEFWRV9BUkNIX0tHREINCiAJc2VsZWN0IEhBVkVfQVJDSF9TRUNDT01QX0ZJTFRFUiBp ZiAoQUVBQkkgJiYgIU9BQklfQ09NUEFUKQ0KZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2luY2x1ZGUv YXNtL2JpdHJldi5oIGIvYXJjaC9hcm0vaW5jbHVkZS9hc20vYml0cmV2LmgNCm5ldyBmaWxlIG1v ZGUgMTAwNjQ0DQppbmRleCAwMDAwMDAwLi5jMjFhNWY0DQotLS0gL2Rldi9udWxsDQorKysgYi9h cmNoL2FybS9pbmNsdWRlL2FzbS9iaXRyZXYuaA0KQEAgLTAsMCArMSwyOCBAQA0KKyNpZm5kZWYg X19BU01fQVJNX0JJVFJFVl9IDQorI2RlZmluZSBfX0FTTV9BUk1fQklUUkVWX0gNCisNCitzdGF0 aWMgX19hbHdheXNfaW5saW5lIF9fYXR0cmlidXRlX2NvbnN0X18gdTMyIF9fYXJjaF9iaXRyZXYz Mih1MzIgeCkNCit7DQorCWlmIChfX2J1aWx0aW5fY29uc3RhbnRfcCh4KSkgew0KKwkJeCA9ICh4 ID4+IDE2KSB8ICh4IDw8IDE2KTsNCisJCXggPSAoKHggJiAweEZGMDBGRjAwKSA+PiA4KSB8ICgo eCAmIDB4MDBGRjAwRkYpIDw8IDgpOw0KKwkJeCA9ICgoeCAmIDB4RjBGMEYwRjApID4+IDQpIHwg KCh4ICYgMHgwRjBGMEYwRikgPDwgNCk7DQorCQl4ID0gKCh4ICYgMHhDQ0NDQ0NDQykgPj4gMikg fCAoKHggJiAweDMzMzMzMzMzKSA8PCAyKTsNCisJCXJldHVybiAoKHggJiAweEFBQUFBQUFBKSA+ PiAxKSB8ICgoeCAmIDB4NTU1NTU1NTUpIDw8IDEpOw0KKwl9DQorCV9fYXNtX18gKCJyYml0ICUw LCAlMSIgOiAiPXIiICh4KSA6ICJyIiAoeCkpOw0KKwlyZXR1cm4geDsNCit9DQorDQorc3RhdGlj IF9fYWx3YXlzX2lubGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUxNiBfX2FyY2hfYml0cmV2MTYo dTE2IHgpDQorew0KKwlyZXR1cm4gX19hcmNoX2JpdHJldjMyKCh1MzIpeCkgPj4gMTY7DQorfQ0K Kw0KK3N0YXRpYyBfX2Fsd2F5c19pbmxpbmUgX19hdHRyaWJ1dGVfY29uc3RfXyB1OCBfX2FyY2hf Yml0cmV2OCh1OCB4KQ0KK3sNCisJcmV0dXJuIF9fYXJjaF9iaXRyZXYzMigodTMyKXgpID4+IDI0 Ow0KK30NCisNCisjZW5kaWYNCisNCi0tIA0KMi4xLjENCg== -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lb0-f182.google.com (mail-lb0-f182.google.com [209.85.217.182]) by kanga.kvack.org (Postfix) with ESMTP id B668B900021 for ; Tue, 28 Oct 2014 23:28:26 -0400 (EDT) Received: by mail-lb0-f182.google.com with SMTP id f15so1882889lbj.41 for ; Tue, 28 Oct 2014 20:28:25 -0700 (PDT) Received: from mail-la0-x22b.google.com (mail-la0-x22b.google.com. [2a00:1450:4010:c03::22b]) by mx.google.com with ESMTPS id bf9si5206510lab.114.2014.10.28.20.28.24 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 20:28:24 -0700 (PDT) Received: by mail-la0-f43.google.com with SMTP id ge10so1806460lab.30 for ; Tue, 28 Oct 2014 20:28:24 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> From: Rob Herring Date: Wed, 29 Oct 2014 11:28:04 +0800 Message-ID: Subject: Re: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: "Wang, Yalin" , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" On Mon, Oct 27, 2014 at 2:46 PM, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: >> this change add CONFIG_HAVE_ARCH_BITREVERSE config option, >> so that we can use arm/arm64 rbit instruction to do bitrev operation >> by hardware. I don't see the original patch in my inbox, so replying here. >> >> Signed-off-by: Yalin Wang >> --- >> arch/arm/Kconfig | 1 + >> arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> include/linux/bitrev.h | 9 +++++++++ >> lib/Kconfig | 9 +++++++++ >> lib/bitrev.c | 2 ++ >> 7 files changed, 64 insertions(+) >> create mode 100644 arch/arm/include/asm/bitrev.h >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index 89c4b5c..426cbcc 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -16,6 +16,7 @@ config ARM >> select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS >> select GENERIC_ALLOCATOR >> select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) >> + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) >> select GENERIC_CLOCKEVENTS_BROADCAST if SMP >> select GENERIC_IDLE_POLL_SETUP >> select GENERIC_IRQ_PROBE [...] >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..263c28c 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -36,6 +36,7 @@ config ARM64 >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> select HAVE_ARCH_JUMP_LABEL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> select HAVE_BPF_JIT The kconfig lists should be sorted. Rob -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by kanga.kvack.org (Postfix) with ESMTP id DF46F900021 for ; Wed, 29 Oct 2014 01:17:10 -0400 (EDT) Received: by mail-pa0-f44.google.com with SMTP id bj1so2422110pad.3 for ; Tue, 28 Oct 2014 22:17:10 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id q14si3041611pdn.220.2014.10.28.22.17.08 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:17:10 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:16:52 +0800 Subject: [RFC V4 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , 'Joe Perches' Cc: 'Russell King - ARM Linux' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" VGhpcyBwYXRjaCBhZGQgYml0cmV2LmggZmlsZSB0byBzdXBwb3J0IHJiaXQgaW5zdHJ1Y3Rpb24s DQpzbyB0aGF0IHdlIGNhbiBkbyBiaXRyZXYgb3BlcmF0aW9uIGJ5IGhhcmR3YXJlLg0KU2lnbmVk LW9mZi1ieTogWWFsaW4gV2FuZyA8eWFsaW4ud2FuZ0Bzb255bW9iaWxlLmNvbT4NCi0tLQ0KIGFy Y2gvYXJtNjQvS2NvbmZpZyAgICAgICAgICAgICAgfCAgMSArDQogYXJjaC9hcm02NC9pbmNsdWRl L2FzbS9iaXRyZXYuaCB8IDI4ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysNCiAyIGZpbGVz IGNoYW5nZWQsIDI5IGluc2VydGlvbnMoKykNCiBjcmVhdGUgbW9kZSAxMDA2NDQgYXJjaC9hcm02 NC9pbmNsdWRlL2FzbS9iaXRyZXYuaA0KDQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9LY29uZmln IGIvYXJjaC9hcm02NC9LY29uZmlnDQppbmRleCA5NTMyZjhkLi5iMWVjMWRkIDEwMDY0NA0KLS0t IGEvYXJjaC9hcm02NC9LY29uZmlnDQorKysgYi9hcmNoL2FybTY0L0tjb25maWcNCkBAIC0zNSw2 ICszNSw3IEBAIGNvbmZpZyBBUk02NA0KIAlzZWxlY3QgSEFORExFX0RPTUFJTl9JUlENCiAJc2Vs ZWN0IEhBUkRJUlFTX1NXX1JFU0VORA0KIAlzZWxlY3QgSEFWRV9BUkNIX0FVRElUU1lTQ0FMTA0K KwlzZWxlY3QgSEFWRV9BUkNIX0JJVFJFVkVSU0UNCiAJc2VsZWN0IEhBVkVfQVJDSF9KVU1QX0xB QkVMDQogCXNlbGVjdCBIQVZFX0FSQ0hfS0dEQg0KIAlzZWxlY3QgSEFWRV9BUkNIX1RSQUNFSE9P Sw0KZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYml0cmV2LmggYi9hcmNoL2Fy bTY0L2luY2x1ZGUvYXNtL2JpdHJldi5oDQpuZXcgZmlsZSBtb2RlIDEwMDY0NA0KaW5kZXggMDAw MDAwMC4uMjkyYTVkZQ0KLS0tIC9kZXYvbnVsbA0KKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL2Fz bS9iaXRyZXYuaA0KQEAgLTAsMCArMSwyOCBAQA0KKyNpZm5kZWYgX19BU01fQVJNNjRfQklUUkVW X0gNCisjZGVmaW5lIF9fQVNNX0FSTTY0X0JJVFJFVl9IDQorDQorc3RhdGljIF9fYWx3YXlzX2lu bGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUzMiBfX2FyY2hfYml0cmV2MzIodTMyIHgpDQorew0K KwlpZiAoX19idWlsdGluX2NvbnN0YW50X3AoeCkpIHsNCisJCXggPSAoeCA+PiAxNikgfCAoeCA8 PCAxNik7DQorCQl4ID0gKCh4ICYgMHhGRjAwRkYwMCkgPj4gOCkgfCAoKHggJiAweDAwRkYwMEZG KSA8PCA4KTsNCisJCXggPSAoKHggJiAweEYwRjBGMEYwKSA+PiA0KSB8ICgoeCAmIDB4MEYwRjBG MEYpIDw8IDQpOw0KKwkJeCA9ICgoeCAmIDB4Q0NDQ0NDQ0MpID4+IDIpIHwgKCh4ICYgMHgzMzMz MzMzMykgPDwgMik7DQorCQlyZXR1cm4gKCh4ICYgMHhBQUFBQUFBQSkgPj4gMSkgfCAoKHggJiAw eDU1NTU1NTU1KSA8PCAxKTsNCisJfQ0KKwlfX2FzbV9fICgicmJpdCAldzAsICV3MSIgOiAiPXIi ICh4KSA6ICJyIiAoeCkpOw0KKwlyZXR1cm4geDsNCit9DQorDQorc3RhdGljIF9fYWx3YXlzX2lu bGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUxNiBfX2FyY2hfYml0cmV2MTYodTE2IHgpDQorew0K KwlyZXR1cm4gX19hcmNoX2JpdHJldjMyKCh1MzIpeCkgPj4gMTY7DQorfQ0KKw0KK3N0YXRpYyBf X2Fsd2F5c19pbmxpbmUgX19hdHRyaWJ1dGVfY29uc3RfXyB1OCBfX2FyY2hfYml0cmV2OCh1OCB4 KQ0KK3sNCisJcmV0dXJuIF9fYXJjaF9iaXRyZXYzMigodTMyKXgpID4+IDI0Ow0KK30NCisNCisj ZW5kaWYNCisNCi0tIA0KMi4xLjENCg== -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by kanga.kvack.org (Postfix) with ESMTP id C33D2900021 for ; Wed, 29 Oct 2014 01:50:43 -0400 (EDT) Received: by mail-pa0-f44.google.com with SMTP id bj1so2443999pad.31 for ; Tue, 28 Oct 2014 22:50:43 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id v5si3085172pdj.234.2014.10.28.22.50.41 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:50:42 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:50:35 +0800 Subject: [RFC V5 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , 'Joe Perches' , 'Russell King - ARM Linux' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" dGhpcyBjaGFuZ2UgYWRkIENPTkZJR19IQVZFX0FSQ0hfQklUUkVWRVJTRSBjb25maWcgb3B0aW9u LA0Kc28gdGhhdCB3ZSBjYW4gdXNlIGFybS9hcm02NCByYml0IGluc3RydWN0aW9uIHRvIGRvIGJp dHJldiBvcGVyYXRpb24NCmJ5IGhhcmR3YXJlLg0KDQpDaGFuZ2UgYml0cmV2MTYoKSBiaXRyZXYz MigpIHRvIGJlIGlubGluZSBmdW5jdGlvbiwNCmRvbid0IG5lZWQgZXhwb3J0IHN5bWJvbCBmb3Ig dGhlc2UgdGlueSBmdW5jdGlvbnMuDQoNClNpZ25lZC1vZmYtYnk6IFlhbGluIFdhbmcgPHlhbGlu LndhbmdAc29ueW1vYmlsZS5jb20+DQotLS0NCiBpbmNsdWRlL2xpbnV4L2JpdHJldi5oIHwgMjEg KysrKysrKysrKysrKysrKysrLS0tDQogbGliL0tjb25maWcgICAgICAgICAgICB8ICA5ICsrKysr KysrKw0KIGxpYi9iaXRyZXYuYyAgICAgICAgICAgfCAxNyArKy0tLS0tLS0tLS0tLS0tLQ0KIDMg ZmlsZXMgY2hhbmdlZCwgMjkgaW5zZXJ0aW9ucygrKSwgMTggZGVsZXRpb25zKC0pDQoNCmRpZmYg LS1naXQgYS9pbmNsdWRlL2xpbnV4L2JpdHJldi5oIGIvaW5jbHVkZS9saW51eC9iaXRyZXYuaA0K aW5kZXggN2ZmZTAzZi4uNDEzYzUyYyAxMDA2NDQNCi0tLSBhL2luY2x1ZGUvbGludXgvYml0cmV2 LmgNCisrKyBiL2luY2x1ZGUvbGludXgvYml0cmV2LmgNCkBAIC0zLDE0ICszLDI5IEBADQogDQog I2luY2x1ZGUgPGxpbnV4L3R5cGVzLmg+DQogDQotZXh0ZXJuIHU4IGNvbnN0IGJ5dGVfcmV2X3Rh YmxlWzI1Nl07DQorI2lmZGVmIENPTkZJR19IQVZFX0FSQ0hfQklUUkVWRVJTRQ0KKyNpbmNsdWRl IDxhc20vYml0cmV2Lmg+DQorDQorI2RlZmluZSBiaXRyZXYzMiBfX2FyY2hfYml0cmV2MzINCisj ZGVmaW5lIGJpdHJldjE2IF9fYXJjaF9iaXRyZXYxNg0KKyNkZWZpbmUgYml0cmV2OCBfX2FyY2hf Yml0cmV2OA0KIA0KKyNlbHNlDQorZXh0ZXJuIHU4IGNvbnN0IGJ5dGVfcmV2X3RhYmxlWzI1Nl07 DQogc3RhdGljIGlubGluZSB1OCBiaXRyZXY4KHU4IGJ5dGUpDQogew0KIAlyZXR1cm4gYnl0ZV9y ZXZfdGFibGVbYnl0ZV07DQogfQ0KIA0KLWV4dGVybiB1MTYgYml0cmV2MTYodTE2IGluKTsNCi1l eHRlcm4gdTMyIGJpdHJldjMyKHUzMiBpbik7DQorc3RhdGljIGlubGluZSB1MTYgYml0cmV2MTYo dTE2IHgpDQorew0KKwlyZXR1cm4gKGJpdHJldjgoeCAmIDB4ZmYpIDw8IDgpIHwgYml0cmV2OCh4 ID4+IDgpOw0KK30NCisNCitzdGF0aWMgaW5saW5lIHUzMiBiaXRyZXYzMih1MzIgeCkNCit7DQor CXJldHVybiAoYml0cmV2MTYoeCAmIDB4ZmZmZikgPDwgMTYpIHwgYml0cmV2MTYoeCA+PiAxNik7 DQorfQ0KIA0KKyNlbmRpZiAvKiBDT05GSUdfSEFWRV9BUkNIX0JJVFJFVkVSU0UgKi8NCiAjZW5k aWYgLyogX0xJTlVYX0JJVFJFVl9IICovDQpkaWZmIC0tZ2l0IGEvbGliL0tjb25maWcgYi9saWIv S2NvbmZpZw0KaW5kZXggNTRjZjMwOS4uY2QxNzdjYSAxMDA2NDQNCi0tLSBhL2xpYi9LY29uZmln DQorKysgYi9saWIvS2NvbmZpZw0KQEAgLTEzLDYgKzEzLDE1IEBAIGNvbmZpZyBSQUlENl9QUQ0K IGNvbmZpZyBCSVRSRVZFUlNFDQogCXRyaXN0YXRlDQogDQorY29uZmlnIEhBVkVfQVJDSF9CSVRS RVZFUlNFDQorCWJvb2xlYW4NCisJZGVmYXVsdCBuDQorCWRlcGVuZHMgb24gQklUUkVWRVJTRQ0K KwloZWxwDQorCSAgVGhpcyBvcHRpb24gcHJvdmlkZXMgYW4gY29uZmlnIGZvciB0aGUgYXJjaGl0 ZWN0dXJlIHdoaWNoIGhhdmUgaW5zdHJ1Y3Rpb24NCisJICBjYW4gZG8gYml0cmV2ZXJzZSBvcGVy YXRpb24sIHdlIHVzZSB0aGUgaGFyZHdhcmUgaW5zdHJ1Y3Rpb24gaWYgdGhlIGFyY2hpdGVjdHVy ZQ0KKwkgIGhhdmUgdGhpcyBjYXBhYmlsaXR5Lg0KKw0KIGNvbmZpZyBSQVRJT05BTA0KIAlib29s ZWFuDQogDQpkaWZmIC0tZ2l0IGEvbGliL2JpdHJldi5jIGIvbGliL2JpdHJldi5jDQppbmRleCAz OTU2MjAzLi40MGZmZGE5IDEwMDY0NA0KLS0tIGEvbGliL2JpdHJldi5jDQorKysgYi9saWIvYml0 cmV2LmMNCkBAIC0xLDMgKzEsNCBAQA0KKyNpZm5kZWYgQ09ORklHX0hBVkVfQVJDSF9CSVRSRVZF UlNFDQogI2luY2x1ZGUgPGxpbnV4L3R5cGVzLmg+DQogI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5o Pg0KICNpbmNsdWRlIDxsaW51eC9iaXRyZXYuaD4NCkBAIC00MiwxOCArNDMsNCBAQCBjb25zdCB1 OCBieXRlX3Jldl90YWJsZVsyNTZdID0gew0KIH07DQogRVhQT1JUX1NZTUJPTF9HUEwoYnl0ZV9y ZXZfdGFibGUpOw0KIA0KLXUxNiBiaXRyZXYxNih1MTYgeCkNCi17DQotCXJldHVybiAoYml0cmV2 OCh4ICYgMHhmZikgPDwgOCkgfCBiaXRyZXY4KHggPj4gOCk7DQotfQ0KLUVYUE9SVF9TWU1CT0wo Yml0cmV2MTYpOw0KLQ0KLS8qKg0KLSAqIGJpdHJldjMyIC0gcmV2ZXJzZSB0aGUgb3JkZXIgb2Yg Yml0cyBpbiBhIHUzMiB2YWx1ZQ0KLSAqIEB4OiB2YWx1ZSB0byBiZSBiaXQtcmV2ZXJzZWQNCi0g Ki8NCi11MzIgYml0cmV2MzIodTMyIHgpDQotew0KLQlyZXR1cm4gKGJpdHJldjE2KHggJiAweGZm ZmYpIDw8IDE2KSB8IGJpdHJldjE2KHggPj4gMTYpOw0KLX0NCi1FWFBPUlRfU1lNQk9MKGJpdHJl djMyKTsNCisjZW5kaWYgLyogQ09ORklHX0hBVkVfQVJDSF9CSVRSRVZFUlNFICovDQotLSANCjIu MS4xDQo= -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by kanga.kvack.org (Postfix) with ESMTP id 3115D900021 for ; Wed, 29 Oct 2014 01:51:30 -0400 (EDT) Received: by mail-pa0-f44.google.com with SMTP id bj1so2445272pad.31 for ; Tue, 28 Oct 2014 22:51:29 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id q7si3168129pdo.134.2014.10.28.22.51.27 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:51:29 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:51:17 +0800 Subject: [RFC V5 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , 'Joe Perches' , 'Russell King - ARM Linux' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" VGhpcyBwYXRjaCBhZGQgYml0cmV2LmggZmlsZSB0byBzdXBwb3J0IHJiaXQgaW5zdHJ1Y3Rpb24s DQpzbyB0aGF0IHdlIGNhbiBkbyBiaXRyZXYgb3BlcmF0aW9uIGJ5IGhhcmR3YXJlLg0KU2lnbmVk LW9mZi1ieTogWWFsaW4gV2FuZyA8eWFsaW4ud2FuZ0Bzb255bW9iaWxlLmNvbT4NCi0tLQ0KIGFy Y2gvYXJtL0tjb25maWcgICAgICAgICAgICAgIHwgIDEgKw0KIGFyY2gvYXJtL2luY2x1ZGUvYXNt L2JpdHJldi5oIHwgMjggKysrKysrKysrKysrKysrKysrKysrKysrKysrKw0KIDIgZmlsZXMgY2hh bmdlZCwgMjkgaW5zZXJ0aW9ucygrKQ0KIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9pbmNs dWRlL2FzbS9iaXRyZXYuaA0KDQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm0vS2NvbmZpZyBiL2FyY2gv YXJtL0tjb25maWcNCmluZGV4IDg5YzRiNWMuLmJlOTJiM2IgMTAwNjQ0DQotLS0gYS9hcmNoL2Fy bS9LY29uZmlnDQorKysgYi9hcmNoL2FybS9LY29uZmlnDQpAQCAtMjgsNiArMjgsNyBAQCBjb25m aWcgQVJNDQogCXNlbGVjdCBIQU5ETEVfRE9NQUlOX0lSUQ0KIAlzZWxlY3QgSEFSRElSUVNfU1df UkVTRU5EDQogCXNlbGVjdCBIQVZFX0FSQ0hfQVVESVRTWVNDQUxMIGlmIChBRUFCSSAmJiAhT0FC SV9DT01QQVQpDQorCXNlbGVjdCBIQVZFX0FSQ0hfQklUUkVWRVJTRSBpZiAoQ1BVX1Y3TSB8fCBD UFVfVjcpDQogCXNlbGVjdCBIQVZFX0FSQ0hfSlVNUF9MQUJFTCBpZiAhWElQX0tFUk5FTA0KIAlz ZWxlY3QgSEFWRV9BUkNIX0tHREINCiAJc2VsZWN0IEhBVkVfQVJDSF9TRUNDT01QX0ZJTFRFUiBp ZiAoQUVBQkkgJiYgIU9BQklfQ09NUEFUKQ0KZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2luY2x1ZGUv YXNtL2JpdHJldi5oIGIvYXJjaC9hcm0vaW5jbHVkZS9hc20vYml0cmV2LmgNCm5ldyBmaWxlIG1v ZGUgMTAwNjQ0DQppbmRleCAwMDAwMDAwLi5jMjFhNWY0DQotLS0gL2Rldi9udWxsDQorKysgYi9h cmNoL2FybS9pbmNsdWRlL2FzbS9iaXRyZXYuaA0KQEAgLTAsMCArMSwyOCBAQA0KKyNpZm5kZWYg X19BU01fQVJNX0JJVFJFVl9IDQorI2RlZmluZSBfX0FTTV9BUk1fQklUUkVWX0gNCisNCitzdGF0 aWMgX19hbHdheXNfaW5saW5lIF9fYXR0cmlidXRlX2NvbnN0X18gdTMyIF9fYXJjaF9iaXRyZXYz Mih1MzIgeCkNCit7DQorCWlmIChfX2J1aWx0aW5fY29uc3RhbnRfcCh4KSkgew0KKwkJeCA9ICh4 ID4+IDE2KSB8ICh4IDw8IDE2KTsNCisJCXggPSAoKHggJiAweEZGMDBGRjAwKSA+PiA4KSB8ICgo eCAmIDB4MDBGRjAwRkYpIDw8IDgpOw0KKwkJeCA9ICgoeCAmIDB4RjBGMEYwRjApID4+IDQpIHwg KCh4ICYgMHgwRjBGMEYwRikgPDwgNCk7DQorCQl4ID0gKCh4ICYgMHhDQ0NDQ0NDQykgPj4gMikg fCAoKHggJiAweDMzMzMzMzMzKSA8PCAyKTsNCisJCXJldHVybiAoKHggJiAweEFBQUFBQUFBKSA+ PiAxKSB8ICgoeCAmIDB4NTU1NTU1NTUpIDw8IDEpOw0KKwl9DQorCV9fYXNtX18gKCJyYml0ICUw LCAlMSIgOiAiPXIiICh4KSA6ICJyIiAoeCkpOw0KKwlyZXR1cm4geDsNCit9DQorDQorc3RhdGlj IF9fYWx3YXlzX2lubGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUxNiBfX2FyY2hfYml0cmV2MTYo dTE2IHgpDQorew0KKwlyZXR1cm4gX19hcmNoX2JpdHJldjMyKCh1MzIpeCkgPj4gMTY7DQorfQ0K Kw0KK3N0YXRpYyBfX2Fsd2F5c19pbmxpbmUgX19hdHRyaWJ1dGVfY29uc3RfXyB1OCBfX2FyY2hf Yml0cmV2OCh1OCB4KQ0KK3sNCisJcmV0dXJuIF9fYXJjaF9iaXRyZXYzMigodTMyKXgpID4+IDI0 Ow0KK30NCisNCisjZW5kaWYNCisNCi0tIA0KMi4xLjENCg== -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by kanga.kvack.org (Postfix) with ESMTP id 3C885900021 for ; Wed, 29 Oct 2014 01:20:24 -0400 (EDT) Received: by mail-pa0-f52.google.com with SMTP id fa1so2398719pad.11 for ; Tue, 28 Oct 2014 22:20:23 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id wm7si2471522pab.216.2014.10.28.22.20.22 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:20:23 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:20:14 +0800 Subject: RE: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18262@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , Joe Perches Cc: Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" PiBGcm9tOiBSb2IgSGVycmluZyBbbWFpbHRvOnJvYmhlcnJpbmcyQGdtYWlsLmNvbV0NCj4gPj4g ZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvS2NvbmZpZyBiL2FyY2gvYXJtNjQvS2NvbmZpZyBpbmRl eA0KPiA+PiA5NTMyZjhkLi4yNjNjMjhjIDEwMDY0NA0KPiA+PiAtLS0gYS9hcmNoL2FybTY0L0tj b25maWcNCj4gPj4gKysrIGIvYXJjaC9hcm02NC9LY29uZmlnDQo+ID4+IEBAIC0zNiw2ICszNiw3 IEBAIGNvbmZpZyBBUk02NA0KPiA+PiAgICAgICBzZWxlY3QgSEFSRElSUVNfU1dfUkVTRU5EDQo+ ID4+ICAgICAgIHNlbGVjdCBIQVZFX0FSQ0hfQVVESVRTWVNDQUxMDQo+ID4+ICAgICAgIHNlbGVj dCBIQVZFX0FSQ0hfSlVNUF9MQUJFTA0KPiA+PiArICAgICBzZWxlY3QgSEFWRV9BUkNIX0JJVFJF VkVSU0UNCj4gPj4gICAgICAgc2VsZWN0IEhBVkVfQVJDSF9LR0RCDQo+ID4+ICAgICAgIHNlbGVj dCBIQVZFX0FSQ0hfVFJBQ0VIT09LDQo+ID4+ICAgICAgIHNlbGVjdCBIQVZFX0JQRl9KSVQNCj4g DQo+IFRoZSBrY29uZmlnIGxpc3RzIHNob3VsZCBiZSBzb3J0ZWQuDQo+IA0KPiBSb2INCg0KR290 IGl0ICwNClRoYW5rcyBmb3IgeW91ciByZW1pbmQuDQo= -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f179.google.com (mail-ig0-f179.google.com [209.85.213.179]) by kanga.kvack.org (Postfix) with ESMTP id 13D9D900021 for ; Wed, 29 Oct 2014 01:21:41 -0400 (EDT) Received: by mail-ig0-f179.google.com with SMTP id r10so2498658igi.0 for ; Tue, 28 Oct 2014 22:21:40 -0700 (PDT) Received: from smtprelay.hostedemail.com (smtprelay0137.hostedemail.com. [216.40.44.137]) by mx.google.com with ESMTP id e8si4913472ioj.65.2014.10.28.22.21.40 for ; Tue, 28 Oct 2014 22:21:40 -0700 (PDT) Message-ID: <1414560096.10912.18.camel@perches.com> Subject: Re: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction From: Joe Perches Date: Tue, 28 Oct 2014 22:21:36 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Rob Herring' , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" On Wed, 2014-10-29 at 13:14 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > We also change byte_rev_table[] to be static, > to make sure no drivers can access it directly. You break the build with this patch. You can't do this until the users of the table are converted. So far, they are not. I submitted patches for these uses, but those patches are not yet applied. Please make sure the dependencies for your patches are explicitly stated. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f44.google.com (mail-pa0-f44.google.com [209.85.220.44]) by kanga.kvack.org (Postfix) with ESMTP id 860006B00BC for ; Wed, 29 Oct 2014 01:36:37 -0400 (EDT) Received: by mail-pa0-f44.google.com with SMTP id bj1so2452018pad.3 for ; Tue, 28 Oct 2014 22:36:37 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id ml2si3137277pab.144.2014.10.28.22.36.35 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:36:36 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:36:30 +0800 Subject: RE: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18263@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <1414560096.10912.18.camel@perches.com> In-Reply-To: <1414560096.10912.18.camel@perches.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Joe Perches' Cc: 'Rob Herring' , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" > From: Joe Perches [mailto:joe@perches.com] > > We also change byte_rev_table[] to be static, to make sure no drivers > > can access it directly. >=20 > You break the build with this patch. >=20 > You can't do this until the users of the table are converted. >=20 > So far, they are not. >=20 > I submitted patches for these uses, but those patches are not yet applied= . >=20 > Please make sure the dependencies for your patches are explicitly stated. >=20 Oh, byte_rev_table[] must be extern, Otherwise, bitrev8() can't access it , I will change it. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f179.google.com (mail-pd0-f179.google.com [209.85.192.179]) by kanga.kvack.org (Postfix) with ESMTP id 0C296900021 for ; Wed, 29 Oct 2014 01:52:09 -0400 (EDT) Received: by mail-pd0-f179.google.com with SMTP id g10so2270301pdj.24 for ; Tue, 28 Oct 2014 22:52:09 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id cl3si3220882pdb.68.2014.10.28.22.52.07 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 28 Oct 2014 22:52:09 -0700 (PDT) From: "Wang, Yalin" Date: Wed, 29 Oct 2014 13:52:00 +0800 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Rob Herring' , 'Joe Perches' , 'Russell King - ARM Linux' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" VGhpcyBwYXRjaCBhZGQgYml0cmV2LmggZmlsZSB0byBzdXBwb3J0IHJiaXQgaW5zdHJ1Y3Rpb24s DQpzbyB0aGF0IHdlIGNhbiBkbyBiaXRyZXYgb3BlcmF0aW9uIGJ5IGhhcmR3YXJlLg0KU2lnbmVk LW9mZi1ieTogWWFsaW4gV2FuZyA8eWFsaW4ud2FuZ0Bzb255bW9iaWxlLmNvbT4NCi0tLQ0KIGFy Y2gvYXJtNjQvS2NvbmZpZyAgICAgICAgICAgICAgfCAgMSArDQogYXJjaC9hcm02NC9pbmNsdWRl L2FzbS9iaXRyZXYuaCB8IDI4ICsrKysrKysrKysrKysrKysrKysrKysrKysrKysNCiAyIGZpbGVz IGNoYW5nZWQsIDI5IGluc2VydGlvbnMoKykNCiBjcmVhdGUgbW9kZSAxMDA2NDQgYXJjaC9hcm02 NC9pbmNsdWRlL2FzbS9iaXRyZXYuaA0KDQpkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9LY29uZmln IGIvYXJjaC9hcm02NC9LY29uZmlnDQppbmRleCA5NTMyZjhkLi5iMWVjMWRkIDEwMDY0NA0KLS0t IGEvYXJjaC9hcm02NC9LY29uZmlnDQorKysgYi9hcmNoL2FybTY0L0tjb25maWcNCkBAIC0zNSw2 ICszNSw3IEBAIGNvbmZpZyBBUk02NA0KIAlzZWxlY3QgSEFORExFX0RPTUFJTl9JUlENCiAJc2Vs ZWN0IEhBUkRJUlFTX1NXX1JFU0VORA0KIAlzZWxlY3QgSEFWRV9BUkNIX0FVRElUU1lTQ0FMTA0K KwlzZWxlY3QgSEFWRV9BUkNIX0JJVFJFVkVSU0UNCiAJc2VsZWN0IEhBVkVfQVJDSF9KVU1QX0xB QkVMDQogCXNlbGVjdCBIQVZFX0FSQ0hfS0dEQg0KIAlzZWxlY3QgSEFWRV9BUkNIX1RSQUNFSE9P Sw0KZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYml0cmV2LmggYi9hcmNoL2Fy bTY0L2luY2x1ZGUvYXNtL2JpdHJldi5oDQpuZXcgZmlsZSBtb2RlIDEwMDY0NA0KaW5kZXggMDAw MDAwMC4uMjkyYTVkZQ0KLS0tIC9kZXYvbnVsbA0KKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL2Fz bS9iaXRyZXYuaA0KQEAgLTAsMCArMSwyOCBAQA0KKyNpZm5kZWYgX19BU01fQVJNNjRfQklUUkVW X0gNCisjZGVmaW5lIF9fQVNNX0FSTTY0X0JJVFJFVl9IDQorDQorc3RhdGljIF9fYWx3YXlzX2lu bGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUzMiBfX2FyY2hfYml0cmV2MzIodTMyIHgpDQorew0K KwlpZiAoX19idWlsdGluX2NvbnN0YW50X3AoeCkpIHsNCisJCXggPSAoeCA+PiAxNikgfCAoeCA8 PCAxNik7DQorCQl4ID0gKCh4ICYgMHhGRjAwRkYwMCkgPj4gOCkgfCAoKHggJiAweDAwRkYwMEZG KSA8PCA4KTsNCisJCXggPSAoKHggJiAweEYwRjBGMEYwKSA+PiA0KSB8ICgoeCAmIDB4MEYwRjBG MEYpIDw8IDQpOw0KKwkJeCA9ICgoeCAmIDB4Q0NDQ0NDQ0MpID4+IDIpIHwgKCh4ICYgMHgzMzMz MzMzMykgPDwgMik7DQorCQlyZXR1cm4gKCh4ICYgMHhBQUFBQUFBQSkgPj4gMSkgfCAoKHggJiAw eDU1NTU1NTU1KSA8PCAxKTsNCisJfQ0KKwlfX2FzbV9fICgicmJpdCAldzAsICV3MSIgOiAiPXIi ICh4KSA6ICJyIiAoeCkpOw0KKwlyZXR1cm4geDsNCit9DQorDQorc3RhdGljIF9fYWx3YXlzX2lu bGluZSBfX2F0dHJpYnV0ZV9jb25zdF9fIHUxNiBfX2FyY2hfYml0cmV2MTYodTE2IHgpDQorew0K KwlyZXR1cm4gX19hcmNoX2JpdHJldjMyKCh1MzIpeCkgPj4gMTY7DQorfQ0KKw0KK3N0YXRpYyBf X2Fsd2F5c19pbmxpbmUgX19hdHRyaWJ1dGVfY29uc3RfXyB1OCBfX2FyY2hfYml0cmV2OCh1OCB4 KQ0KK3sNCisJcmV0dXJuIF9fYXJjaF9iaXRyZXYzMigodTMyKXgpID4+IDI0Ow0KK30NCisNCisj ZW5kaWYNCisNCi0tIA0KMi4xLjENCg== -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by kanga.kvack.org (Postfix) with ESMTP id E7A4690008B for ; Thu, 30 Oct 2014 08:01:38 -0400 (EDT) Received: by mail-pa0-f52.google.com with SMTP id fa1so5335272pad.11 for ; Thu, 30 Oct 2014 05:01:38 -0700 (PDT) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id gh6si6479142pac.73.2014.10.30.05.01.37 for ; Thu, 30 Oct 2014 05:01:37 -0700 (PDT) Date: Thu, 30 Oct 2014 12:01:27 +0000 From: Will Deacon Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> Content-Language: en-US Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Rob Herring' , 'Joe Perches' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > 2 files changed, 29 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..292a5de > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); Shouldn't this part be in the generic code? > + } > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); You can write this more neatly as: asm ("rbit %w0, %w0" : "+r" (x)); Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-la0-f42.google.com (mail-la0-f42.google.com [209.85.215.42]) by kanga.kvack.org (Postfix) with ESMTP id B6C6790008B for ; Thu, 30 Oct 2014 08:26:46 -0400 (EDT) Received: by mail-la0-f42.google.com with SMTP id gq15so4305772lab.29 for ; Thu, 30 Oct 2014 05:26:46 -0700 (PDT) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com. [209.85.217.174]) by mx.google.com with ESMTPS id zk2si11813260lbb.51.2014.10.30.05.26.43 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 05:26:43 -0700 (PDT) Received: by mail-lb0-f174.google.com with SMTP id z11so2257770lbi.33 for ; Thu, 30 Oct 2014 05:26:43 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> Date: Thu, 30 Oct 2014 13:26:42 +0100 Message-ID: Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction From: Ard Biesheuvel Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: Will Deacon Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" On 30 October 2014 13:01, Will Deacon wrote: > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: >> This patch add bitrev.h file to support rbit instruction, >> so that we can do bitrev operation by hardware. >> Signed-off-by: Yalin Wang >> --- >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 29 insertions(+) >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..b1ec1dd 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -35,6 +35,7 @@ config ARM64 >> select HANDLE_DOMAIN_IRQ >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_JUMP_LABEL >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h >> new file mode 100644 >> index 0000000..292a5de >> --- /dev/null >> +++ b/arch/arm64/include/asm/bitrev.h >> @@ -0,0 +1,28 @@ >> +#ifndef __ASM_ARM64_BITREV_H >> +#define __ASM_ARM64_BITREV_H >> + >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) >> +{ >> + if (__builtin_constant_p(x)) { >> + x = (x >> 16) | (x << 16); >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > Shouldn't this part be in the generic code? > >> + } >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > You can write this more neatly as: > > asm ("rbit %w0, %w0" : "+r" (x)); > This forces GCC to use the same register as input and output, which doesn't necessarily result in the fastest code. (e.g., if the un-bitrev()'ed value is reused again afterwards). On the other hand, the original notation does allow GCC to use the same register, but doesn't force it to, so I prefer the original one. -- Ard. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f173.google.com (mail-pd0-f173.google.com [209.85.192.173]) by kanga.kvack.org (Postfix) with ESMTP id 9CC0790008B for ; Thu, 30 Oct 2014 09:57:55 -0400 (EDT) Received: by mail-pd0-f173.google.com with SMTP id v10so5224236pde.32 for ; Thu, 30 Oct 2014 06:57:55 -0700 (PDT) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id bl1si6661795pad.160.2014.10.30.06.57.54 for ; Thu, 30 Oct 2014 06:57:54 -0700 (PDT) Date: Thu, 30 Oct 2014 13:57:49 +0000 From: Will Deacon Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141030135749.GE32589@arm.com> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: owner-linux-mm@kvack.org List-ID: To: Ard Biesheuvel Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" On Thu, Oct 30, 2014 at 12:26:42PM +0000, Ard Biesheuvel wrote: > On 30 October 2014 13:01, Will Deacon wrote: > > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > >> This patch add bitrev.h file to support rbit instruction, > >> so that we can do bitrev operation by hardware. > >> Signed-off-by: Yalin Wang > >> --- > >> arch/arm64/Kconfig | 1 + > >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > >> 2 files changed, 29 insertions(+) > >> create mode 100644 arch/arm64/include/asm/bitrev.h > >> > >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > >> index 9532f8d..b1ec1dd 100644 > >> --- a/arch/arm64/Kconfig > >> +++ b/arch/arm64/Kconfig > >> @@ -35,6 +35,7 @@ config ARM64 > >> select HANDLE_DOMAIN_IRQ > >> select HARDIRQS_SW_RESEND > >> select HAVE_ARCH_AUDITSYSCALL > >> + select HAVE_ARCH_BITREVERSE > >> select HAVE_ARCH_JUMP_LABEL > >> select HAVE_ARCH_KGDB > >> select HAVE_ARCH_TRACEHOOK > >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > >> new file mode 100644 > >> index 0000000..292a5de > >> --- /dev/null > >> +++ b/arch/arm64/include/asm/bitrev.h > >> @@ -0,0 +1,28 @@ > >> +#ifndef __ASM_ARM64_BITREV_H > >> +#define __ASM_ARM64_BITREV_H > >> + > >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > >> +{ > >> + if (__builtin_constant_p(x)) { > >> + x = (x >> 16) | (x << 16); > >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > > Shouldn't this part be in the generic code? > > > >> + } > >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > > > You can write this more neatly as: > > > > asm ("rbit %w0, %w0" : "+r" (x)); > > > > This forces GCC to use the same register as input and output, which > doesn't necessarily result in the fastest code. (e.g., if the > un-bitrev()'ed value is reused again afterwards). > On the other hand, the original notation does allow GCC to use the > same register, but doesn't force it to, so I prefer the original one. That's a good point, especially since this is __always_inline. Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f50.google.com (mail-pa0-f50.google.com [209.85.220.50]) by kanga.kvack.org (Postfix) with ESMTP id B74DB280022 for ; Fri, 31 Oct 2014 01:40:30 -0400 (EDT) Received: by mail-pa0-f50.google.com with SMTP id eu11so7067217pac.9 for ; Thu, 30 Oct 2014 22:40:30 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id fn9si8367892pdb.160.2014.10.30.22.40.26 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 22:40:29 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 13:40:20 +0800 Subject: [RFC V6 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> In-Reply-To: <20141030135749.GE32589@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , Ard Biesheuvel Cc: Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use some architecture's bitrev hardware instruction to do bitrev operation. Introduce __constant_bitrev* macro for constant bitrev operation. Change __bitrev16() __bitrev32() to be inline function, don't need export symbol for these tiny functions. Signed-off-by: Yalin Wang --- include/linux/bitrev.h | 77 ++++++++++++++++++++++++++++++++++++++++++++++= +--- lib/Kconfig | 9 ++++++ lib/bitrev.c | 17 ++--------- 3 files changed, 84 insertions(+), 19 deletions(-) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..fb790b8 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,14 +3,83 @@ =20 #include =20 -extern u8 const byte_rev_table[256]; +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define __bitrev32 __arch_bitrev32 +#define __bitrev16 __arch_bitrev16 +#define __bitrev8 __arch_bitrev8 =20 -static inline u8 bitrev8(u8 byte) +#else +extern u8 const byte_rev_table[256]; +static inline u8 __bitrev8(u8 byte) { return byte_rev_table[byte]; } =20 -extern u16 bitrev16(u16 in); -extern u32 bitrev32(u32 in); +static inline u16 __bitrev16(u16 x) +{ + return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8); +} + +static inline u32 __bitrev32(u32 x) +{ + return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16); +} + +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ + +#define __constant_bitrev32(x) \ +({ \ + u32 __x =3D x; \ + __x =3D (__x >> 16) | (__x << 16); \ + __x =3D ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) << = 8); \ + __x =3D ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << = 4); \ + __x =3D ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << = 2); \ + __x =3D ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << = 1); \ + __x; \ +}) + +#define __constant_bitrev16(x) \ +({ \ + u16 __x =3D x; \ + __x =3D (__x >> 8) | (__x << 8); \ + __x =3D ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4); \ + __x =3D ((__x & (u16)0xCCCCU) >> 2) | ((__x & (u16)0x3333U) << 2); \ + __x =3D ((__x & (u16)0xAAAAU) >> 1) | ((__x & (u16)0x5555U) << 1); \ + __x; \ +}) + +#define __constant_bitrev8(x) \ +({ \ + u8 __x =3D x; \ + __x =3D (__x >> 4) | (__x << 4); \ + __x =3D ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2); \ + __x =3D ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1); \ + __x; \ +}) + +#define bitrev32(x) \ +({ \ + u32 __x =3D x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev32(__x) : \ + __bitrev32(__x); \ +}) + +#define bitrev16(x) \ +({ \ + u16 __x =3D x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev16(__x) : \ + __bitrev16(__x); \ + }) =20 +#define bitrev8(x) \ +({ \ + u8 __x =3D x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev8(__x) : \ + __bitrev8(__x) ; \ + }) #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate =20 +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruct= ion + can do bitreverse operation, we use the hardware instruction if the arc= hitecture + have this capability. + config RATIONAL boolean =20 diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..40ffda9 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -42,18 +43,4 @@ const u8 byte_rev_table[256] =3D { }; EXPORT_SYMBOL_GPL(byte_rev_table); =20 -u16 bitrev16(u16 x) -{ - return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); -} -EXPORT_SYMBOL(bitrev16); - -/** - * bitrev32 - reverse the order of bits in a u32 value - * @x: value to be bit-reversed - */ -u32 bitrev32(u32 x) -{ - return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); -} -EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by kanga.kvack.org (Postfix) with ESMTP id E27DA280022 for ; Fri, 31 Oct 2014 01:41:02 -0400 (EDT) Received: by mail-pd0-f169.google.com with SMTP id y10so6599023pdj.14 for ; Thu, 30 Oct 2014 22:41:02 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id hp10si8401910pad.114.2014.10.30.22.41.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 22:41:02 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 13:40:55 +0800 Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' Cc: 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..e9b2571 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f171.google.com (mail-pd0-f171.google.com [209.85.192.171]) by kanga.kvack.org (Postfix) with ESMTP id 1D01F280018 for ; Thu, 30 Oct 2014 22:03:35 -0400 (EDT) Received: by mail-pd0-f171.google.com with SMTP id r10so6297686pdi.2 for ; Thu, 30 Oct 2014 19:03:34 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id qk1si7970588pac.189.2014.10.30.19.03.32 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 19:03:34 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 10:03:27 +0800 Subject: RE: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1826F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> In-Reply-To: <20141030120127.GC32589@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' Cc: 'Rob Herring' , 'Joe Perches' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: Thursday, October 30, 2014 8:01 PM > To: Wang, Yalin > Cc: 'Rob Herring'; 'Joe Perches'; 'Russell King - ARM Linux'; 'linux- > kernel@vger.kernel.org'; 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; > 'linux-arm-kernel@lists.infradead.org' > Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit > instruction >=20 > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x =3D (x >> 16) | (x << 16); > > + x =3D ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x =3D ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x =3D ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); >=20 > Shouldn't this part be in the generic code? Good idea, I will change this part into linux/bitrev.h . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f49.google.com (mail-pa0-f49.google.com [209.85.220.49]) by kanga.kvack.org (Postfix) with ESMTP id 3DF91280022 for ; Fri, 31 Oct 2014 01:41:55 -0400 (EDT) Received: by mail-pa0-f49.google.com with SMTP id lj1so6912167pab.8 for ; Thu, 30 Oct 2014 22:41:54 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id tl10si8464218pac.46.2014.10.30.22.41.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 22:41:54 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 13:41:48 +0800 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' Cc: 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..b1ec1dd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitre= v.h new file mode 100644 index 0000000..706a209 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM64_BITREV_H +#define __ASM_ARM64_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f51.google.com (mail-pa0-f51.google.com [209.85.220.51]) by kanga.kvack.org (Postfix) with ESMTP id 78EEB280022 for ; Fri, 31 Oct 2014 01:42:59 -0400 (EDT) Received: by mail-pa0-f51.google.com with SMTP id kq14so7052220pab.10 for ; Thu, 30 Oct 2014 22:42:59 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id c3si8484857pat.15.2014.10.30.22.42.56 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 30 Oct 2014 22:42:58 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 13:42:44 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , 'Ard Biesheuvel' Cc: 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..e9b2571 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f46.google.com (mail-pa0-f46.google.com [209.85.220.46]) by kanga.kvack.org (Postfix) with ESMTP id 4830228001C for ; Fri, 31 Oct 2014 03:40:53 -0400 (EDT) Received: by mail-pa0-f46.google.com with SMTP id lf10so7131317pab.5 for ; Fri, 31 Oct 2014 00:40:52 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id kg10si2820997pad.184.2014.10.31.00.40.51 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 00:40:52 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 15:40:46 +0800 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), because uprobe_notify_resume() have do this. Signed-off-by: Yalin Wang --- arch/arm/kernel/signal.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index bd19834..ff598f0 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thr= ead_flags, int syscall) return restart; } syscall =3D 0; - } else if (thread_flags & _TIF_UPROBE) { - clear_thread_flag(TIF_UPROBE); + } else if (thread_flags & _TIF_UPROBE) uprobe_notify_resume(regs); - } else { + else { clear_thread_flag(TIF_NOTIFY_RESUME); tracehook_notify_resume(regs); } --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f171.google.com (mail-ig0-f171.google.com [209.85.213.171]) by kanga.kvack.org (Postfix) with ESMTP id 516CE28001C for ; Fri, 31 Oct 2014 03:45:39 -0400 (EDT) Received: by mail-ig0-f171.google.com with SMTP id hl2so458666igb.16 for ; Fri, 31 Oct 2014 00:45:39 -0700 (PDT) Received: from smtprelay.hostedemail.com (smtprelay0221.hostedemail.com. [216.40.44.221]) by mx.google.com with ESMTP id d7si14374612igg.40.2014.10.31.00.45.38 for ; Fri, 31 Oct 2014 00:45:38 -0700 (PDT) Message-ID: <1414741535.8928.2.camel@perches.com> Subject: Re: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) From: Joe Perches Date: Fri, 31 Oct 2014 00:45:35 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Fri, 2014-10-31 at 15:40 +0800, Wang, Yalin wrote: > This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), > because uprobe_notify_resume() have do this. [] > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c [] > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) > return restart; > } > syscall = 0; > - } else if (thread_flags & _TIF_UPROBE) { > - clear_thread_flag(TIF_UPROBE); > + } else if (thread_flags & _TIF_UPROBE) > uprobe_notify_resume(regs); > - } else { > + else { > clear_thread_flag(TIF_NOTIFY_RESUME); > tracehook_notify_resume(regs); > } Please keep the braces. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by kanga.kvack.org (Postfix) with ESMTP id 622EC280031 for ; Fri, 31 Oct 2014 04:01:20 -0400 (EDT) Received: by mail-pd0-f169.google.com with SMTP id y10so6820632pdj.28 for ; Fri, 31 Oct 2014 01:01:20 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id rj8si8598155pdb.192.2014.10.31.01.01.18 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 01:01:19 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 16:01:13 +0800 Subject: [RFC V2] arm:remove clear_thread_flag(TIF_UPROBE) Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827F@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), because uprobe_notify_resume() have do this. Signed-off-by: Yalin Wang --- arch/arm/kernel/signal.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index bd19834..8aa6f1b 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -592,7 +592,6 @@ do_work_pending(struct pt_regs *regs, unsigned int thre= ad_flags, int syscall) } syscall =3D 0; } else if (thread_flags & _TIF_UPROBE) { - clear_thread_flag(TIF_UPROBE); uprobe_notify_resume(regs); } else { clear_thread_flag(TIF_NOTIFY_RESUME); --=20 2.1.1 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f178.google.com (mail-pd0-f178.google.com [209.85.192.178]) by kanga.kvack.org (Postfix) with ESMTP id C8A5B28001C for ; Fri, 31 Oct 2014 03:51:48 -0400 (EDT) Received: by mail-pd0-f178.google.com with SMTP id fp1so6776319pdb.37 for ; Fri, 31 Oct 2014 00:51:48 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id dh6si8716429pdb.26.2014.10.31.00.51.46 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 00:51:48 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 15:51:41 +0800 Subject: RE: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> In-Reply-To: <1414741535.8928.2.camel@perches.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Joe Perches' Cc: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" > From: Joe Perches [mailto:joe@perches.com] > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > [] > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > thread_flags, int syscall) > > return restart; > > } > > syscall =3D 0; > > - } else if (thread_flags & _TIF_UPROBE) { > > - clear_thread_flag(TIF_UPROBE); > > + } else if (thread_flags & _TIF_UPROBE) > > uprobe_notify_resume(regs); > > - } else { > > + else { > > clear_thread_flag(TIF_NOTIFY_RESUME); > > tracehook_notify_resume(regs); > > } >=20 > Please keep the braces. mm.. could I know the reason ? :) Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f173.google.com (mail-pd0-f173.google.com [209.85.192.173]) by kanga.kvack.org (Postfix) with ESMTP id EF3DF28001C for ; Fri, 31 Oct 2014 03:54:24 -0400 (EDT) Received: by mail-pd0-f173.google.com with SMTP id v10so6821268pde.32 for ; Fri, 31 Oct 2014 00:54:24 -0700 (PDT) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id kz15si5617891pab.192.2014.10.31.00.54.22 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 00:54:23 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 15:54:16 +0800 Subject: RE: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827D@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , 'Ard Biesheuvel' Cc: 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > From: Wang, Yalin > Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit > instruction >=20 > This patch add bitrev.h file to support rbit instruction, so that we can = do > bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h >=20 > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b > 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git > a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file > mode 100644 index 0000000..e9b2571 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) { > + __asm__ ("rbit %0, %1" : "=3Dr" (x) : "r" (x)); > + return x; > +} > + > +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) { > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) { > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > -- > 2.1.1 Wrong title, please ignore this one , I have resend another [RFC V6 2/3] . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f179.google.com (mail-ie0-f179.google.com [209.85.223.179]) by kanga.kvack.org (Postfix) with ESMTP id D21A8280031 for ; Fri, 31 Oct 2014 03:58:13 -0400 (EDT) Received: by mail-ie0-f179.google.com with SMTP id rl12so734594iec.24 for ; Fri, 31 Oct 2014 00:58:13 -0700 (PDT) Received: from smtprelay.hostedemail.com (smtprelay0107.hostedemail.com. [216.40.44.107]) by mx.google.com with ESMTP id kz2si14389142icb.89.2014.10.31.00.58.13 for ; Fri, 31 Oct 2014 00:58:13 -0700 (PDT) Message-ID: <1414742289.8928.5.camel@perches.com> Subject: Re: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) From: Joe Perches Date: Fri, 31 Oct 2014 00:58:09 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Fri, 2014-10-31 at 15:51 +0800, Wang, Yalin wrote: > > From: Joe Perches [mailto:joe@perches.com] > > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > > [] > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > > thread_flags, int syscall) > > > return restart; > > > } > > > syscall = 0; > > > - } else if (thread_flags & _TIF_UPROBE) { > > > - clear_thread_flag(TIF_UPROBE); > > > + } else if (thread_flags & _TIF_UPROBE) > > > uprobe_notify_resume(regs); > > > - } else { > > > + else { > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > tracehook_notify_resume(regs); > > > } > > > > Please keep the braces. > > mm.. could I know the reason ? :) Try read Documentation/CodingStyle Chapter 3: Placing Braces and Spaces use braces in both branches: if (condition) { do_this(); do_that(); } else { otherwise(); } -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f176.google.com (mail-pd0-f176.google.com [209.85.192.176]) by kanga.kvack.org (Postfix) with ESMTP id EEEF5280031 for ; Fri, 31 Oct 2014 03:59:44 -0400 (EDT) Received: by mail-pd0-f176.google.com with SMTP id ft15so6802229pdb.21 for ; Fri, 31 Oct 2014 00:59:44 -0700 (PDT) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id bf4si8619292pdb.162.2014.10.31.00.59.42 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 31 Oct 2014 00:59:44 -0700 (PDT) From: "Wang, Yalin" Date: Fri, 31 Oct 2014 15:59:37 +0800 Subject: RE: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827E@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> <1414742289.8928.5.camel@perches.com> In-Reply-To: <1414742289.8928.5.camel@perches.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Joe Perches' Cc: 'Will Deacon' , 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" > From: Joe Perches [mailto:joe@perches.com] > > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned > int > > > thread_flags, int syscall) > > > > return restart; > > > > } > > > > syscall =3D 0; > > > > - } else if (thread_flags & _TIF_UPROBE) { > > > > - clear_thread_flag(TIF_UPROBE); > > > > + } else if (thread_flags & _TIF_UPROBE) > > > > uprobe_notify_resume(regs); > > > > - } else { > > > > + else { > > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > > tracehook_notify_resume(regs); > > > > } > > > > > > Please keep the braces. > > > > mm.. could I know the reason ? :) >=20 > Try read Documentation/CodingStyle >=20 > Chapter 3: Placing Braces and Spaces >=20 > use braces in both branches: >=20 > if (condition) { > do_this(); > do_that(); > } else { > otherwise(); > } >=20 Got it, I will resend one . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qg0-f45.google.com (mail-qg0-f45.google.com [209.85.192.45]) by kanga.kvack.org (Postfix) with ESMTP id E74BC28001E for ; Fri, 31 Oct 2014 06:43:21 -0400 (EDT) Received: by mail-qg0-f45.google.com with SMTP id z107so5365808qgd.32 for ; Fri, 31 Oct 2014 03:43:21 -0700 (PDT) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id j4si4401947qai.6.2014.10.31.03.43.20 for ; Fri, 31 Oct 2014 03:43:21 -0700 (PDT) Date: Fri, 31 Oct 2014 10:43:06 +0000 From: Will Deacon Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141031104305.GC6731@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Fri, Oct 31, 2014 at 05:41:48AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..706a209 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H Really minor nit, but we don't tend to include 'ARM64' in our header guards, so this should just be __ASM_BITREV_H. With that change, Acked-by: Will Deacon Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by kanga.kvack.org (Postfix) with ESMTP id B05C56B011A for ; Sun, 2 Nov 2014 21:17:23 -0500 (EST) Received: by mail-pd0-f169.google.com with SMTP id y10so10721525pdj.0 for ; Sun, 02 Nov 2014 18:17:23 -0800 (PST) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id rb7si14243077pab.142.2014.11.02.18.17.20 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 02 Nov 2014 18:17:22 -0800 (PST) From: "Wang, Yalin" Date: Mon, 3 Nov 2014 10:17:15 +0800 Subject: RE: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> In-Reply-To: <20141031104305.GC6731@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' Cc: 'Ard Biesheuvel' , 'Russell King - ARM Linux' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > From: Will Deacon [mailto:will.deacon@arm.com] > > +#ifndef __ASM_ARM64_BITREV_H > > +#define __ASM_ARM64_BITREV_H >=20 > Really minor nit, but we don't tend to include 'ARM64' in our header guar= ds, > so this should just be __ASM_BITREV_H. >=20 > With that change, >=20 > Acked-by: Will Deacon >=20 I have send the patch to the patch system: http://www.arm.linux.org.uk/developer/patches/search.php?uid=3D4025 8187/1 8188/1 8189/1 Just remind you that , should also cherry-pick Joe Perches's=20 2 patches: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 To make sure there is no build error when build these 2 drivers. Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lb0-f182.google.com (mail-lb0-f182.google.com [209.85.217.182]) by kanga.kvack.org (Postfix) with ESMTP id C53016B010B for ; Mon, 3 Nov 2014 03:47:34 -0500 (EST) Received: by mail-lb0-f182.google.com with SMTP id f15so9918078lbj.27 for ; Mon, 03 Nov 2014 00:47:33 -0800 (PST) Received: from mail-la0-f52.google.com (mail-la0-f52.google.com. [209.85.215.52]) by mx.google.com with ESMTPS id tb1si31460176lbb.130.2014.11.03.00.47.33 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Nov 2014 00:47:33 -0800 (PST) Received: by mail-la0-f52.google.com with SMTP id pv20so7378442lab.11 for ; Mon, 03 Nov 2014 00:47:33 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> Date: Mon, 3 Nov 2014 09:47:32 +0100 Message-ID: Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction From: Ard Biesheuvel Content-Type: text/plain; charset=UTF-8 Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: Will Deacon , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" On 3 November 2014 03:17, Wang, Yalin wrote: >> From: Will Deacon [mailto:will.deacon@arm.com] >> > +#ifndef __ASM_ARM64_BITREV_H >> > +#define __ASM_ARM64_BITREV_H >> >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, >> so this should just be __ASM_BITREV_H. >> >> With that change, >> >> Acked-by: Will Deacon >> > I have send the patch to the patch system: > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > 8187/1 8188/1 8189/1 > > Just remind you that , should also cherry-pick Joe Perches's > 2 patches: > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > To make sure there is no build error when build these 2 drivers. > If this is the case, I suggest you update patch 8187/1 to retain the byte_rev_table symbol, even in the accelerated case, and remove it with a followup patch once Joe's patches have landed upstream. Also, a link to the patches would be nice, and perhaps a bit of explanation how/when they are expected to be merged. -- Ard. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f172.google.com (mail-pd0-f172.google.com [209.85.192.172]) by kanga.kvack.org (Postfix) with ESMTP id BAFAE6B00A3 for ; Mon, 3 Nov 2014 04:50:56 -0500 (EST) Received: by mail-pd0-f172.google.com with SMTP id r10so11244503pdi.31 for ; Mon, 03 Nov 2014 01:50:56 -0800 (PST) Received: from foss-mx-na.foss.arm.com (foss-mx-na.foss.arm.com. [217.140.108.86]) by mx.google.com with ESMTP id gq2si14839950pbc.217.2014.11.03.01.50.54 for ; Mon, 03 Nov 2014 01:50:55 -0800 (PST) Date: Mon, 3 Nov 2014 09:50:51 +0000 From: Will Deacon Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141103095051.GA23019@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: owner-linux-mm@kvack.org List-ID: To: Ard Biesheuvel Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" On Mon, Nov 03, 2014 at 08:47:32AM +0000, Ard Biesheuvel wrote: > On 3 November 2014 03:17, Wang, Yalin wrote: > >> From: Will Deacon [mailto:will.deacon@arm.com] > >> > +#ifndef __ASM_ARM64_BITREV_H > >> > +#define __ASM_ARM64_BITREV_H > >> > >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, > >> so this should just be __ASM_BITREV_H. > >> > >> With that change, > >> > >> Acked-by: Will Deacon > >> > > I have send the patch to the patch system: > > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > > > 8187/1 8188/1 8189/1 > > > > Just remind you that , should also cherry-pick Joe Perches's > > 2 patches: > > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > > > To make sure there is no build error when build these 2 drivers. > > > > If this is the case, I suggest you update patch 8187/1 to retain the > byte_rev_table symbol, even in the accelerated case, and remove it > with a followup patch once Joe's patches have landed upstream. Also, a > link to the patches would be nice, and perhaps a bit of explanation > how/when they are expected to be merged. Indeed, or instead put together a series with the appropriate acks so somebody can merge it all in one go. Merging this on a piecemeal basis is going to cause breakages (as you pointed out). Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by kanga.kvack.org (Postfix) with ESMTP id 70D5E6B0099 for ; Mon, 3 Nov 2014 20:45:50 -0500 (EST) Received: by mail-pa0-f52.google.com with SMTP id fa1so13361657pad.11 for ; Mon, 03 Nov 2014 17:45:50 -0800 (PST) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id gt8si16707025pbc.42.2014.11.03.17.45.47 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Nov 2014 17:45:48 -0800 (PST) From: "Wang, Yalin" Date: Tue, 4 Nov 2014 09:45:42 +0800 Subject: RE: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18288@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> <20141103095051.GA23019@arm.com> In-Reply-To: <20141103095051.GA23019@arm.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Will Deacon' , Ard Biesheuvel Cc: Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" > From: Will Deacon [mailto:will.deacon@arm.com] > > > > If this is the case, I suggest you update patch 8187/1 to retain the > > byte_rev_table symbol, even in the accelerated case, and remove it > > with a followup patch once Joe's patches have landed upstream. Also, a > > link to the patches would be nice, and perhaps a bit of explanation > > how/when they are expected to be merged. >=20 > Indeed, or instead put together a series with the appropriate acks so > somebody can merge it all in one go. Merging this on a piecemeal basis is > going to cause breakages (as you pointed out). >=20 > Will Hi Will, Could I add you as ack-by , and submit these 2 patches into the Patch system ? So you can merge them together . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f53.google.com (mail-wg0-f53.google.com [74.125.82.53]) by kanga.kvack.org (Postfix) with ESMTP id 8EFB96B00D4 for ; Thu, 13 Nov 2014 18:53:36 -0500 (EST) Received: by mail-wg0-f53.google.com with SMTP id b13so18039039wgh.12 for ; Thu, 13 Nov 2014 15:53:36 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id dz13si46737846wjb.100.2014.11.13.15.53.35 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 13 Nov 2014 15:53:35 -0800 (PST) Date: Thu, 13 Nov 2014 23:53:22 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..be92b3b 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) Looking at this, this is just wrong. Take a moment to consider what happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. What happens if an ARMv6 CPU tries to execute an rbit instruction? Second point (which isn't obvious from your submissions on-list) is that you've loaded the patch system up with patches for other parts of the kernel tree for which I am not responsible for. As such, I can't take those patches without the sub-tree maintainer acking them. Also, the commit text in those patches look weird: 6fire: Convert byte_rev_table uses to bitrev8 Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches <(address hidden)> Signed-off-by: Yalin Wang <(address hidden)> Why is Joe signing off on these patches? As his is the first sign-off, one assumes that he was responsible for creating the patch in the first place, but there is no From: line marking him as the author. Shouldn't his entry be an Acked-by: ? Confused. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f172.google.com (mail-ig0-f172.google.com [209.85.213.172]) by kanga.kvack.org (Postfix) with ESMTP id 2D88C6B00D2 for ; Thu, 13 Nov 2014 19:05:35 -0500 (EST) Received: by mail-ig0-f172.google.com with SMTP id a13so593899igq.17 for ; Thu, 13 Nov 2014 16:05:34 -0800 (PST) Received: from smtprelay.hostedemail.com (smtprelay0249.hostedemail.com. [216.40.44.249]) by mx.google.com with ESMTP id mx4si1202101igb.20.2014.11.13.16.05.33 for ; Thu, 13 Nov 2014 16:05:34 -0800 (PST) Message-ID: <1415923530.4223.17.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches Date: Thu, 13 Nov 2014 16:05:30 -0800 In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Russell King - ARM Linux , Takashi Iwai Cc: "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, > > so that we can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: > > 6fire: Convert byte_rev_table uses to bitrev8 > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit > reversals to eliminate the array. > > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> > > Why is Joe signing off on these patches? > Shouldn't his entry be an Acked-by: ? I didn't sign off on or ack the "add bitrev.h" patch. I created 2 patches that converted direct uses of byte_rev_table to that bitrev8 static inline. One of them is already in -next 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 The other hasn't been applied. https://lkml.org/lkml/2014/10/28/1056 Maybe Takashi Iwai will get around to it one day. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by kanga.kvack.org (Postfix) with ESMTP id 11FBE6B00D2 for ; Thu, 13 Nov 2014 19:17:39 -0500 (EST) Received: by mail-wg0-f43.google.com with SMTP id y10so18302754wgg.16 for ; Thu, 13 Nov 2014 16:17:38 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id pn10si46836551wjb.77.2014.11.13.16.17.38 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 13 Nov 2014 16:17:38 -0800 (PST) Date: Fri, 14 Nov 2014 00:17:21 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114001720.GD4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415923530.4223.17.camel@perches.com> Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. Correct, I never said you did. Please read my message a bit more carefully next time, huh? > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. Great, so I can just discard these that were incorrectly submitted to me then. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f169.google.com (mail-ie0-f169.google.com [209.85.223.169]) by kanga.kvack.org (Postfix) with ESMTP id 3A3006B00D2 for ; Thu, 13 Nov 2014 19:45:49 -0500 (EST) Received: by mail-ie0-f169.google.com with SMTP id y20so89126ier.14 for ; Thu, 13 Nov 2014 16:45:48 -0800 (PST) Received: from smtprelay.hostedemail.com (smtprelay0188.hostedemail.com. [216.40.44.188]) by mx.google.com with ESMTP id m6si42384209icf.58.2014.11.13.16.45.47 for ; Thu, 13 Nov 2014 16:45:47 -0800 (PST) Message-ID: <1415925943.4141.1.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches Date: Thu, 13 Nov 2014 16:45:43 -0800 In-Reply-To: <20141114001720.GD4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Russell King - ARM Linux Cc: Takashi Iwai , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > Correct, I never said you did. Please read my message a bit more carefully > next time, huh? You've no reason to write that Russell. I'm not trying to be anything other than clear and no I didn't say you said that either. Why not make your own writing clearer or your own memory sharper then eh? Reply on the patch I actually wrote. You were cc'd on it when I submitted it. > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > Great, so I can just discard these that were incorrectly submitted to me > then. I think you shouldn't apply these patches or updated ones either until all the current uses are converted. cheers, Joe -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f169.google.com (mail-wi0-f169.google.com [209.85.212.169]) by kanga.kvack.org (Postfix) with ESMTP id 2F6576B00DC for ; Thu, 13 Nov 2014 20:18:53 -0500 (EST) Received: by mail-wi0-f169.google.com with SMTP id n3so3741790wiv.0 for ; Thu, 13 Nov 2014 17:18:52 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id n7si1512450wic.31.2014.11.13.17.18.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 13 Nov 2014 17:18:51 -0800 (PST) Date: Fri, 14 Nov 2014 01:18:32 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114011832.GE4042@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415925943.4141.1.camel@perches.com> Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > Correct, I never said you did. Please read my message a bit more carefully > > next time, huh? > > You've no reason to write that Russell. Absolutely I have, but I'm not going to discuss it because I'll just end up flaming you because in my mind you are the one who is completely mistaken with your comments. In case it hasn't been realised, I hardly read this mailing list anymore, or messages that I'm Cc'd on. I do read most messages that I'm in the To: line, but generally not if they're DT changes (which always end up being marked To: me.) > > Great, so I can just discard these that were incorrectly submitted to me > > then. > > I think you shouldn't apply these patches or updated > ones either until all the current uses are converted. Where are the dependencies mentioned? How do I get to know when all the dependencies are met? Who is tracking the dependencies? -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f171.google.com (mail-ie0-f171.google.com [209.85.223.171]) by kanga.kvack.org (Postfix) with ESMTP id 239356B00E0 for ; Thu, 13 Nov 2014 20:26:49 -0500 (EST) Received: by mail-ie0-f171.google.com with SMTP id x19so17008062ier.16 for ; Thu, 13 Nov 2014 17:26:48 -0800 (PST) Received: from smtprelay.hostedemail.com (smtprelay0196.hostedemail.com. [216.40.44.196]) by mx.google.com with ESMTP id bg1si39402958icb.41.2014.11.13.17.26.47 for ; Thu, 13 Nov 2014 17:26:48 -0800 (PST) Message-ID: <1415928394.4141.3.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches Date: Thu, 13 Nov 2014 17:26:34 -0800 In-Reply-To: <20141114011832.GE4042@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Russell King - ARM Linux Cc: Takashi Iwai , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > I think you shouldn't apply these patches or updated > > ones either until all the current uses are converted. > > Where are the dependencies mentioned? I mentioned it when these patches (which are not mine btw), were submitted the second time. https://lkml.org/lkml/2014/10/27/69 > How do I get to know when all > the dependencies are met? No idea. > Who is tracking the dependencies? Not me. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pa0-f51.google.com (mail-pa0-f51.google.com [209.85.220.51]) by kanga.kvack.org (Postfix) with ESMTP id 297A96B00E6 for ; Thu, 13 Nov 2014 21:01:42 -0500 (EST) Received: by mail-pa0-f51.google.com with SMTP id kq14so16589708pab.38 for ; Thu, 13 Nov 2014 18:01:41 -0800 (PST) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id sv10si15426080pab.161.2014.11.13.18.01.39 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 13 Nov 2014 18:01:40 -0800 (PST) From: "Wang, Yalin" Date: Fri, 14 Nov 2014 10:01:34 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, November 14, 2014 7:53 AM > To: Wang, Yalin > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, so that we > > can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) >=20 > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? Is it possible to build a kernel that support both CPU_V6 and CPU_V7? I mean in Kconfig, CPU_V6 =3D y and CPU_V7 =3D y ? If there is problem like you said, How about this solution: select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) =20 > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: >=20 > 6fire: Convert byte_rev_table uses to bitrev8 >=20 > Use the inline function instead of directly indexing the array. >=20 > This allows some architectures with hardware instructions for bit reversa= ls > to eliminate the array. >=20 > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> >=20 > Why is Joe signing off on these patches? As his is the first sign-off, o= ne > assumes that he was responsible for creating the patch in the first place= , > but there is no From: line marking him as the author. Shouldn't his entr= y > be an Acked-by: ? >=20 > Confused. For this patch, I just cherry-pick from Joe, If you are not responsible for this part, I will submit to the maintainers for these patches . Sorry for that . -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com [209.85.212.179]) by kanga.kvack.org (Postfix) with ESMTP id 367BF6B00D3 for ; Fri, 14 Nov 2014 01:37:16 -0500 (EST) Received: by mail-wi0-f179.google.com with SMTP id ex7so1678294wid.6 for ; Thu, 13 Nov 2014 22:37:15 -0800 (PST) Received: from mx2.suse.de (cantor2.suse.de. [195.135.220.15]) by mx.google.com with ESMTPS id ju9si2204924wid.94.2014.11.13.22.37.14 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 13 Nov 2014 22:37:14 -0800 (PST) Date: Fri, 14 Nov 2014 07:37:13 +0100 Message-ID: From: Takashi Iwai Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415923530.4223.17.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: Russell King - ARM Linux , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" At Thu, 13 Nov 2014 16:05:30 -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. > > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. It was not clear to me whether I should apply it individually from others in the whole thread. Your description looked as if it makes sense only with ARM's bitrev8 support. So, again: should I apply this now to my tree? Takashi -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by kanga.kvack.org (Postfix) with ESMTP id 7371E6B00D3 for ; Fri, 14 Nov 2014 01:55:14 -0500 (EST) Received: by mail-ie0-f182.google.com with SMTP id rd18so17372840iec.27 for ; Thu, 13 Nov 2014 22:55:14 -0800 (PST) Received: from smtprelay.hostedemail.com (smtprelay0033.hostedemail.com. [216.40.44.33]) by mx.google.com with ESMTP id d198si40243358iod.76.2014.11.13.22.55.12 for ; Thu, 13 Nov 2014 22:55:13 -0800 (PST) Message-ID: <1415948109.5912.12.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches Date: Thu, 13 Nov 2014 22:55:09 -0800 In-Reply-To: References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> Content-Type: text/plain; charset="ISO-8859-1" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: owner-linux-mm@kvack.org List-ID: To: Takashi Iwai Cc: Russell King - ARM Linux , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > At Thu, 13 Nov 2014 16:05:30 -0800, > Joe Perches wrote: > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > It was not clear to me whether I should apply it individually from > others in the whole thread. Your description looked as if it makes > sense only with ARM's bitrev8 support. > > So, again: should I apply this now to my tree? I it would be good to apply even if the bitrev patch for arm is never applied. $ git grep -w bitrev8 | wc -l 110 vs this last direct use of byte_rev_table. cheers, Joe -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f173.google.com (mail-wi0-f173.google.com [209.85.212.173]) by kanga.kvack.org (Postfix) with ESMTP id 55A966B00D4 for ; Fri, 14 Nov 2014 02:03:03 -0500 (EST) Received: by mail-wi0-f173.google.com with SMTP id n3so1713946wiv.12 for ; Thu, 13 Nov 2014 23:03:02 -0800 (PST) Received: from mx2.suse.de (cantor2.suse.de. [195.135.220.15]) by mx.google.com with ESMTPS id hj4si47807405wjc.122.2014.11.13.23.03.02 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 13 Nov 2014 23:03:02 -0800 (PST) Date: Fri, 14 Nov 2014 08:03:01 +0100 Message-ID: From: Takashi Iwai Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415948109.5912.12.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <1415948109.5912.12.camel@perches.com> MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: Russell King - ARM Linux , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" At Thu, 13 Nov 2014 22:55:09 -0800, Joe Perches wrote: > > On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > > At Thu, 13 Nov 2014 16:05:30 -0800, > > Joe Perches wrote: > > > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > > > I created 2 patches that converted direct uses of byte_rev_table > > > to that bitrev8 static inline. One of them is already in -next > > > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > > > The other hasn't been applied. > > > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > > > Maybe Takashi Iwai will get around to it one day. > > > > It was not clear to me whether I should apply it individually from > > others in the whole thread. Your description looked as if it makes > > sense only with ARM's bitrev8 support. > > > > So, again: should I apply this now to my tree? > > I it would be good to apply even if the > bitrev patch for arm is never applied. > > $ git grep -w bitrev8 | wc -l > 110 > > vs > > this last direct use of byte_rev_table. Alright, I picked up your original patch and merged. thanks, Takashi -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by kanga.kvack.org (Postfix) with ESMTP id C8A916B00EA for ; Fri, 14 Nov 2014 04:52:23 -0500 (EST) Received: by mail-wg0-f50.google.com with SMTP id k14so895902wgh.9 for ; Fri, 14 Nov 2014 01:52:23 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id fl5si3000083wib.10.2014.11.14.01.52.22 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Nov 2014 01:52:22 -0800 (PST) Date: Fri, 14 Nov 2014 09:52:06 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114095205.GF4042@n2100.arm.linux.org.uk> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> <1415928394.4141.3.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415928394.4141.3.camel@perches.com> Sender: owner-linux-mm@kvack.org List-ID: To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" On Thu, Nov 13, 2014 at 05:26:34PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > > I think you shouldn't apply these patches or updated > > > ones either until all the current uses are converted. > > > > Where are the dependencies mentioned? > > I mentioned it when these patches (which are not > mine btw), were submitted the second time. Yes, I'm well aware that the author of the ARM patches are Yalin Wang. > https://lkml.org/lkml/2014/10/27/69 > > > How do I get to know when all > > the dependencies are met? > > No idea. > > > Who is tracking the dependencies? > > Not me. Right, what that means is that no one is doing that. What you've also said in this thread now is that the ARM patches should not be applied until all the other users are converted. As those patches are going via other trees, that means the ARM patches can only be applied _after_ the next merge window _if_ all maintainers pick up the previous set. As I'm not tracking the status of what other maintainers do, I'm simply going to avoid applying these patches until after the next merge window and hope that the other maintainers pick the dependent patches up and get them in during the next merge window. If not, I guess we'll see compile breakage. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wg0-f50.google.com (mail-wg0-f50.google.com [74.125.82.50]) by kanga.kvack.org (Postfix) with ESMTP id B468D6B00ED for ; Fri, 14 Nov 2014 04:58:27 -0500 (EST) Received: by mail-wg0-f50.google.com with SMTP id k14so908229wgh.9 for ; Fri, 14 Nov 2014 01:58:27 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id bq18si2991804wib.25.2014.11.14.01.58.26 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Nov 2014 01:58:26 -0800 (PST) Date: Fri, 14 Nov 2014 09:58:12 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114095812.GG4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Fri, Nov 14, 2014 at 10:01:34AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > Sent: Friday, November 14, 2014 7:53 AM > > To: Wang, Yalin > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, so that we > > > can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > > 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? Absolutely it is. > I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? Yes. > If there is problem like you said, > How about this solution: > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) That would work. > For this patch, > I just cherry-pick from Joe, > If you are not responsible for this part, > I will submit to the maintainers for these patches . > Sorry for that . I think you need to discuss with Joe how Joe would like his patches handled. However, it seems that Joe already sent his patches to the appropriate maintainers, and they have been applying those patches themselves. Since your generic ARM changes depend on these patches being accepted first, this means is that I can't apply the generic ARM changes until those other patches have hit mainline, otherwise things are going to break. So, when you come to submit the latest set of patches to the patch system, please do so only after these dependent patches have been merged into mainline so that they don't get accidentally applied before hand and break the two drivers that Joe mentioned. Thanks. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pd0-f182.google.com (mail-pd0-f182.google.com [209.85.192.182]) by kanga.kvack.org (Postfix) with ESMTP id 4384C6B0069 for ; Sun, 16 Nov 2014 21:39:10 -0500 (EST) Received: by mail-pd0-f182.google.com with SMTP id g10so5168267pdj.27 for ; Sun, 16 Nov 2014 18:39:09 -0800 (PST) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id gn9si33992153pac.127.2014.11.16.18.39.07 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 16 Nov 2014 18:39:08 -0800 (PST) From: "Wang, Yalin" Date: Mon, 17 Nov 2014 10:38:58 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> In-Reply-To: <20141114095812.GG4042@n2100.arm.linux.org.uk> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, November 14, 2014 5:58 PM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm= - > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instructi= on > > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? >=20 > Absolutely it is. >=20 > > I mean in Kconfig, CPU_V6 =3D y and CPU_V7 =3D y ? >=20 > Yes. >=20 > > If there is problem like you said, > > How about this solution: > > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) >=20 > That would work. >=20 OK, I will submit a patch for this change. > > For this patch, > > I just cherry-pick from Joe, > > If you are not responsible for this part, I will submit to the > > maintainers for these patches . > > Sorry for that . >=20 > I think you need to discuss with Joe how Joe would like his patches handl= ed. > However, it seems that Joe already sent his patches to the appropriate > maintainers, and they have been applying those patches themselves. >=20 > Since your generic ARM changes depend on these patches being accepted fir= st, > this means is that I can't apply the generic ARM changes until those othe= r > patches have hit mainline, otherwise things are going to break. So, when > you come to submit the latest set of patches to the patch system, please = do > so only after these dependent patches have been merged into mainline so > that they don't get accidentally applied before hand and break the two > drivers that Joe mentioned. Joe has submitted patches to maintainers, So we need wait for them to be accepted . Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f173.google.com (mail-wi0-f173.google.com [209.85.212.173]) by kanga.kvack.org (Postfix) with ESMTP id 4C5C16B0038 for ; Thu, 8 Jan 2015 13:41:14 -0500 (EST) Received: by mail-wi0-f173.google.com with SMTP id r20so5161913wiv.0 for ; Thu, 08 Jan 2015 10:41:13 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id p5si13749322wjp.121.2015.01.08.10.41.13 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 08 Jan 2015 10:41:13 -0800 (PST) Date: Thu, 8 Jan 2015 18:40:59 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150108184059.GZ12302@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > Joe has submitted patches to maintainers, > So we need wait for them to be accepted . I ran these patches through my autobuilder, and while most builds didn't seem to be a problem, the randconfigs found errors: /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode `rbit r3,r2' /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode `rbit r0,r1' make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode `rbit r2,r2' make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode `rbit r2,r2' /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode `rbit r1,r1' /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode `rbit r3,r3' /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode `rbit r5,r5' /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 The root cause is that the kernel being built is supposed to support both ARMv7 and ARMv6K CPUs. However, "rbit" is only available on ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ie0-f181.google.com (mail-ie0-f181.google.com [209.85.223.181]) by kanga.kvack.org (Postfix) with ESMTP id EA22A6B0038 for ; Thu, 8 Jan 2015 21:17:13 -0500 (EST) Received: by mail-ie0-f181.google.com with SMTP id rl12so12812670iec.12 for ; Thu, 08 Jan 2015 18:17:13 -0800 (PST) Received: from cnbjrel01.sonyericsson.com (cnbjrel01.sonyericsson.com. [219.141.167.165]) by mx.google.com with ESMTPS id it7si5720097icc.75.2015.01.08.18.17.10 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 08 Jan 2015 18:17:12 -0800 (PST) From: "Wang, Yalin" Date: Fri, 9 Jan 2015 10:16:32 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> In-Reply-To: <20150108184059.GZ12302@n2100.arm.linux.org.uk> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' Cc: 'Will Deacon' , 'Ard Biesheuvel' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, January 09, 2015 2:41 AM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm= - > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instructi= on >=20 > On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > > Joe has submitted patches to maintainers, So we need wait for them to > > be accepted . >=20 > I ran these patches through my autobuilder, and while most builds didn't > seem to be a problem, the randconfigs found errors: >=20 > /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode > `rbit r3,r2' > /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode > `rbit r0,r1' > make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 >=20 > /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode > `rbit r2,r2' > make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 >=20 > /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode > `rbit r2,r2' > /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 >=20 > /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode > `rbit r1,r1' > /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode > `rbit r3,r3' > /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode > `rbit r5,r5' > /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 >=20 > The root cause is that the kernel being built is supposed to support both > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. >=20 In the patch that you applied: 8205/1 add bitrev.h file to support rbit instruction I have add : + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) If you build kernel support ARMv6K, should CONFIG_CPU_V6=3Dy, isn't it ? Then will not build hardware rbit instruction, isn't it ? Thanks -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f172.google.com (mail-wi0-f172.google.com [209.85.212.172]) by kanga.kvack.org (Postfix) with ESMTP id 99FEF6B0038 for ; Fri, 9 Jan 2015 06:11:05 -0500 (EST) Received: by mail-wi0-f172.google.com with SMTP id n3so1532023wiv.5 for ; Fri, 09 Jan 2015 03:11:05 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id dg2si3278085wib.98.2015.01.09.03.11.04 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 09 Jan 2015 03:11:04 -0800 (PST) Date: Fri, 9 Jan 2015 11:10:48 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150109111048.GE12302@n2100.arm.linux.org.uk> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Ard Biesheuvel' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > Sent: Friday, January 09, 2015 2:41 AM > > To: Wang, Yalin > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > > kernel@lists.infradead.org' > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > > > The root cause is that the kernel being built is supposed to support both > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > In the patch that you applied: > 8205/1 add bitrev.h file to support rbit instruction > > I have add : > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? > Then will not build hardware rbit instruction, isn't it ? The config has: CONFIG_CPU_PJ4=y # CONFIG_CPU_V6 is not set CONFIG_CPU_V6K=y CONFIG_CPU_V7=y CONFIG_CPU_32v6=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y And no, the CONFIG_CPU_V* flags refer to the CPUs. The CONFIG_CPU_32v* symbols refer to the CPU architectures. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ob0-f177.google.com (mail-ob0-f177.google.com [209.85.214.177]) by kanga.kvack.org (Postfix) with ESMTP id 7F1C26B0038 for ; Fri, 9 Jan 2015 07:41:34 -0500 (EST) Received: by mail-ob0-f177.google.com with SMTP id va2so12506462obc.8 for ; Fri, 09 Jan 2015 04:41:34 -0800 (PST) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id oz5si5348004oeb.95.2015.01.09.04.41.30 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 09 Jan 2015 04:41:32 -0800 (PST) From: "Wang, Yalin" Date: Fri, 9 Jan 2015 20:40:56 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> In-Reply-To: <20150109111048.GE12302@n2100.arm.linux.org.uk> Content-Language: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' Cc: 'Ard Biesheuvel' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, January 09, 2015 7:11 PM > To: Wang, Yalin > Cc: 'Ard Biesheuvel'; 'Will Deacon'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm= - > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instructi= on >=20 > On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > > -----Original Message----- > > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > > Sent: Friday, January 09, 2015 2:41 AM > > > To: Wang, Yalin > > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > > > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; > > > 'linux-arm- kernel@lists.infradead.org' > > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit > > > instruction > > > > > > The root cause is that the kernel being built is supposed to support > > > both > > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > > > In the patch that you applied: > > 8205/1 add bitrev.h file to support rbit instruction > > > > I have add : > > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=3Dy, isn't it = ? > > Then will not build hardware rbit instruction, isn't it ? >=20 > The config has: >=20 > CONFIG_CPU_PJ4=3Dy > # CONFIG_CPU_V6 is not set > CONFIG_CPU_V6K=3Dy > CONFIG_CPU_V7=3Dy > CONFIG_CPU_32v6=3Dy > CONFIG_CPU_32v6K=3Dy > CONFIG_CPU_32v7=3Dy >=20 > And no, the CONFIG_CPU_V* flags refer to the CPUs. The > CONFIG_CPU_32v* symbols refer to the CPU architectures. >=20 Oh, I see, How about change like this: + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6= K) I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&= =1B$B!!=1B(B!CPU_ARM940T ? Another solution is: + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && != CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) By the way, I am not clear about the difference between CPU_V6 and CPU_V6K,= could you tell me? :) Thank you=20 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-la0-f47.google.com (mail-la0-f47.google.com [209.85.215.47]) by kanga.kvack.org (Postfix) with ESMTP id 241266B0032 for ; Wed, 14 Jan 2015 11:38:18 -0500 (EST) Received: by mail-la0-f47.google.com with SMTP id hz20so9094253lab.6 for ; Wed, 14 Jan 2015 08:38:17 -0800 (PST) Received: from pandora.arm.linux.org.uk (pandora.arm.linux.org.uk. [2001:4d48:ad52:3201:214:fdff:fe10:1be6]) by mx.google.com with ESMTPS id cx2si27044861wib.101.2015.01.14.08.38.16 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 14 Jan 2015 08:38:16 -0800 (PST) Date: Wed, 14 Jan 2015 16:38:00 +0000 From: Russell King - ARM Linux Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150114163800.GZ12302@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> Sender: owner-linux-mm@kvack.org List-ID: To: "Wang, Yalin" Cc: 'Ard Biesheuvel' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" On Fri, Jan 09, 2015 at 08:40:56PM +0800, Wang, Yalin wrote: > Oh, I see, > How about change like this: > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6K) > I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&a??!CPU_ARM940T ? > > Another solution is: > + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) > > By the way, I am not clear about the difference between CPU_V6 and CPU_V6K, could you tell me? :) I think select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 is sufficient - we don't support mixing pre-v6 and v6+ CPU architectures into a single kernel. -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ig0-f182.google.com (mail-ig0-f182.google.com [209.85.213.182]) by kanga.kvack.org (Postfix) with ESMTP id 387EF6B0032 for ; Thu, 15 Jan 2015 21:05:55 -0500 (EST) Received: by mail-ig0-f182.google.com with SMTP id hn15so1193013igb.3 for ; Thu, 15 Jan 2015 18:05:55 -0800 (PST) Received: from cnbjrel02.sonyericsson.com (cnbjrel02.sonyericsson.com. [219.141.167.166]) by mx.google.com with ESMTPS id e3si806489igx.29.2015.01.15.18.05.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 15 Jan 2015 18:05:54 -0800 (PST) From: "Wang, Yalin" Date: Fri, 16 Jan 2015 09:42:23 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E1B0@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> <20150114163800.GZ12302@n2100.arm.linux.org.uk> In-Reply-To: <20150114163800.GZ12302@n2100.arm.linux.org.uk> Content-Language: en-US Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 Sender: owner-linux-mm@kvack.org List-ID: To: 'Russell King - ARM Linux' Cc: 'Ard Biesheuvel' , 'Will Deacon' , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , 'Joe Perches' , "'linux-arm-kernel@lists.infradead.org'" PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiBGcm9tOiBSdXNzZWxsIEtpbmcgLSBBUk0g TGludXggW21haWx0bzpsaW51eEBhcm0ubGludXgub3JnLnVrXQ0KPiBTZW50OiBUaHVyc2RheSwg SmFudWFyeSAxNSwgMjAxNSAxMjozOCBBTQ0KPiBUbzogV2FuZywgWWFsaW4NCj4gQ2M6ICdBcmQg Qmllc2hldXZlbCc7ICdXaWxsIERlYWNvbic7ICdsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3Jn JzsNCj4gJ2FraW5vYnUubWl0YUBnbWFpbC5jb20nOyAnbGludXgtbW1Aa3ZhY2sub3JnJzsgJ0pv ZSBQZXJjaGVzJzsgJ2xpbnV4LWFybS0NCj4ga2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcnDQo+ IFN1YmplY3Q6IFJlOiBbUkZDIFY2IDIvM10gYXJtOmFkZCBiaXRyZXYuaCBmaWxlIHRvIHN1cHBv cnQgcmJpdCBpbnN0cnVjdGlvbg0KPiANCj4gT24gRnJpLCBKYW4gMDksIDIwMTUgYXQgMDg6NDA6 NTZQTSArMDgwMCwgV2FuZywgWWFsaW4gd3JvdGU6DQo+ID4gT2gsIEkgc2VlLA0KPiA+IEhvdyBh Ym91dCBjaGFuZ2UgbGlrZSB0aGlzOg0KPiA+ICsJc2VsZWN0IEhBVkVfQVJDSF9CSVRSRVZFUlNF IGlmICgoQ1BVX1Y3TSB8fCBDUFVfVjcpICYmICFDUFVfVjYgJiYNCj4gPiArIUNQVV9WNkspDQo+ ID4gSSBhbSBub3Qgc3VyZSBpZiBJIGFsc28gbmVlZCBhZGQgc29tZSBvbGRlciBDUFUgdHlwZXMg bGlrZSAhQ1BVX0FSTTlURE1JDQo+ICYm44CAIUNQVV9BUk05NDBUID8NCj4gPg0KPiA+IEFub3Ro ZXIgc29sdXRpb24gaXM6DQo+ID4gKwlzZWxlY3QgSEFWRV9BUkNIX0JJVFJFVkVSU0UgaWYgKChD UFVfMzJWN00gfHwgQ1BVXzMyVjcpICYmICFDUFVfMzJWNg0KPiA+ICsmJiAhQ1BVXzMyVjUgJiYg IUNQVV8zMlY0ICYmICFDUFVfMzJWNFQgJiYgIUNQVV8zMlYzKQ0KPiA+DQo+ID4gQnkgdGhlIHdh eSwgSSBhbSBub3QgY2xlYXIgYWJvdXQgdGhlIGRpZmZlcmVuY2UgYmV0d2VlbiBDUFVfVjYgYW5k DQo+ID4gQ1BVX1Y2SywgY291bGQgeW91IHRlbGwgbWU/IDopDQo+IA0KPiBJIHRoaW5rDQo+IA0K PiAJc2VsZWN0IEhBVkVfQVJDSF9CSVRSRVZFUlNFIGlmIChDUFVfMzJ2N00gfHwgQ1BVXzMydjcp ICYmICFDUFVfMzJ2Ng0KPiANCj4gaXMgc3VmZmljaWVudCAtIHdlIGRvbid0IHN1cHBvcnQgbWl4 aW5nIHByZS12NiBhbmQgdjYrIENQVSBhcmNoaXRlY3R1cmVzDQo+IGludG8gYSBzaW5nbGUga2Vy bmVsLg0KPiANCk9rLCBJIHdpbGwgcmUtc2VuZCBhIHBhdGNoLiANCg0KVGhhbmtzDQo= -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754674AbaJXFKk (ORCPT ); Fri, 24 Oct 2014 01:10:40 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:11602 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751733AbaJXFKi convert rfc822-to-8bit (ORCPT ); Fri, 24 Oct 2014 01:10:38 -0400 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Fri, 24 Oct 2014 13:10:33 +0800 Subject: [PATCH RFC] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit Thread-Topic: [PATCH RFC] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit Thread-Index: Ac/vSNa3pqIFIz3+QkO0bxiJmBEKOg== Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 8 ++++++++ lib/bitrev.c | 2 ++ 7 files changed, 63 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..0df5866 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index ac9afde..a2566d7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..5d24c11 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ #include +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..e0e0453 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,14 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751769AbaJ0Gie (ORCPT ); Mon, 27 Oct 2014 02:38:34 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:7227 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751141AbaJ0Gic convert rfc822-to-8bit (ORCPT ); Mon, 27 Oct 2014 02:38:32 -0400 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Mon, 27 Oct 2014 14:37:28 +0800 Subject: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/vSNa3pqIFIz3+QkO0bxiJmBEKOgCZ3qpA Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 9 +++++++++ lib/bitrev.c | 2 ++ 7 files changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..0df5866 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..263c28c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -36,6 +36,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..5d24c11 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ #include +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751962AbaJ0GqP (ORCPT ); Mon, 27 Oct 2014 02:46:15 -0400 Received: from smtprelay0004.hostedemail.com ([216.40.44.4]:49397 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751605AbaJ0GqO (ORCPT ); Mon, 27 Oct 2014 02:46:14 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::,RULES_HIT:41:355:379:541:599:800:960:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1431:1437:1515:1516:1518:1534:1543:1593:1594:1711:1730:1747:1777:1792:1801:2194:2199:2393:2559:2562:2828:3138:3139:3140:3141:3142:3355:3622:3865:3866:3867:3868:3870:3871:3874:4321:4605:5007:6119:6120:6261:7903:10004:10400:10848:11026:11232:11473:11657:11658:11914:12043:12114:12291:12296:12438:12517:12519:12555:12740:13255:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: leg38_362f2ebf9f505 X-Filterd-Recvd-Size: 4914 Message-ID: <1414392371.8884.2.camel@perches.com> Subject: Re: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction From: Joe Perches To: "Wang, Yalin" Cc: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Sun, 26 Oct 2014 23:46:11 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 64 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..0df5866 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..263c28c 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -36,6 +36,7 @@ config ARM64 > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > select HAVE_ARCH_JUMP_LABEL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > select HAVE_BPF_JIT > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..5d24c11 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static inline __attribute_const__ u16 __arch_bitrev16(u16 x) > +{ > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static inline __attribute_const__ u8 __arch_bitrev8(u8 x) > +{ > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > index 7ffe03f..ef5b2bb 100644 > --- a/include/linux/bitrev.h > +++ b/include/linux/bitrev.h > @@ -3,6 +3,14 @@ > > #include > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > +#include > + > +#define bitrev32 __arch_bitrev32 > +#define bitrev16 __arch_bitrev16 > +#define bitrev8 __arch_bitrev8 > + > +#else > extern u8 const byte_rev_table[256]; If this is done, the direct uses of byte_rev_table in drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c should be converted too? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752399AbaJ0HNz (ORCPT ); Mon, 27 Oct 2014 03:13:55 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:10942 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751752AbaJ0HNy convert rfc822-to-8bit (ORCPT ); Mon, 27 Oct 2014 03:13:54 -0400 From: "Wang, Yalin" To: "'Joe Perches'" CC: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Mon, 27 Oct 2014 15:13:50 +0800 Subject: RE: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/xsbWsvpUYtHz/QbmB40QKeJ42aAAA7E+A Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18258@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: <1414392371.8884.2.camel@perches.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > If this is done, the direct uses of byte_rev_table in > drivers/net/wireless/ath/carl9170/phy.c and sound/usb/6fire/firmware.c > should be converted too? > I think use bitrev8() is safer than to use byte_rev_table[] directly. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752211AbaJ0ICW (ORCPT ); Mon, 27 Oct 2014 04:02:22 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:12237 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751562AbaJ0ICU convert rfc822-to-8bit (ORCPT ); Mon, 27 Oct 2014 04:02:20 -0400 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Mon, 27 Oct 2014 16:02:08 +0800 Subject: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/vSNa3pqIFIz3+QkO0bxiJmBEKOgCZ3qpAAALvvtA= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ include/linux/bitrev.h | 9 +++++++++ lib/Kconfig | 9 +++++++++ lib/bitrev.c | 2 ++ 7 files changed, 78 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..426cbcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,6 +16,7 @@ config ARM select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS select GENERIC_ALLOCATOR select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_IDLE_POLL_SETUP select GENERIC_IRQ_PROBE diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..c21a5f4 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..263c28c 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -36,6 +36,7 @@ config ARM64 select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_JUMP_LABEL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK select HAVE_BPF_JIT diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..f725a71 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..ef5b2bb 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,6 +3,14 @@ #include +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else extern u8 const byte_rev_table[256]; static inline u8 bitrev8(u8 byte) @@ -13,4 +21,5 @@ static inline u8 bitrev8(u8 byte) extern u16 bitrev16(u16 in); extern u32 bitrev32(u32 in); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..93d637a 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -57,3 +58,4 @@ u32 bitrev32(u32 x) return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); } EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751778AbaJ0KtE (ORCPT ); Mon, 27 Oct 2014 06:49:04 -0400 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:48864 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751141AbaJ0KtB (ORCPT ); Mon, 27 Oct 2014 06:49:01 -0400 Date: Mon, 27 Oct 2014 10:48:48 +0000 From: Will Deacon To: "Wang, Yalin" Cc: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Subject: Re: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <20141027104848.GD8768@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 27, 2014 at 08:02:08AM +0000, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > include/linux/bitrev.h | 9 +++++++++ > lib/Kconfig | 9 +++++++++ > lib/bitrev.c | 2 ++ > 7 files changed, 78 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..426cbcc 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -16,6 +16,7 @@ config ARM > select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS > select GENERIC_ALLOCATOR > select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_IDLE_POLL_SETUP > select GENERIC_IRQ_PROBE > diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h > new file mode 100644 > index 0000000..c21a5f4 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > + } > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64-bit register. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752840AbaJ1Bes (ORCPT ); Mon, 27 Oct 2014 21:34:48 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:16900 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750780AbaJ1Ber convert rfc822-to-8bit (ORCPT ); Mon, 27 Oct 2014 21:34:47 -0400 From: "Wang, Yalin" To: "'Will Deacon'" CC: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Tue, 28 Oct 2014 09:34:42 +0800 Subject: RE: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/x06hnK3vlP4BiRju1caxUbUunAgAe3XOw Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> In-Reply-To: <20141027104848.GD8768@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Will Deacon [mailto:will.deacon@arm.com] > > +++ b/arch/arm/include/asm/bitrev.h > > @@ -0,0 +1,28 @@ > > +#ifndef __ASM_ARM_BITREV_H > > +#define __ASM_ARM_BITREV_H > > + > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x = (x >> 16) | (x << 16); > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > + } > > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64- > bit register. For arm64 in arch/arm64/include/asm/bitrev.h. I have use __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); For arm , I use __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); Am I right ? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753064AbaJ1N7w (ORCPT ); Tue, 28 Oct 2014 09:59:52 -0400 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:49747 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751074AbaJ1N7v (ORCPT ); Tue, 28 Oct 2014 09:59:51 -0400 Date: Tue, 28 Oct 2014 13:59:44 +0000 From: Will Deacon To: "Wang, Yalin" Cc: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Subject: Re: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Message-ID: <20141028135944.GC29706@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 28, 2014 at 01:34:42AM +0000, Wang, Yalin wrote: > > From: Will Deacon [mailto:will.deacon@arm.com] > > > +++ b/arch/arm/include/asm/bitrev.h > > > @@ -0,0 +1,28 @@ > > > +#ifndef __ASM_ARM_BITREV_H > > > +#define __ASM_ARM_BITREV_H > > > + > > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > > +{ > > > + if (__builtin_constant_p(x)) { > > > + x = (x >> 16) | (x << 16); > > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > + } > > > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > > > > I think you need to use %w0 and %w1 here, otherwise you bit-reverse the 64- > > bit register. > For arm64 in arch/arm64/include/asm/bitrev.h. > I have use __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > For arm , I use __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > Am I right ? Yup, sorry, I didn't realise this patch covered both architectures. It would probably be a good idea to split it into 3 parts: a core part, then the two architectural bits. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753641AbaJ1VXz (ORCPT ); Tue, 28 Oct 2014 17:23:55 -0400 Received: from smtprelay0077.hostedemail.com ([216.40.44.77]:56522 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751377AbaJ1VXy (ORCPT ); Tue, 28 Oct 2014 17:23:54 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::::::::::,RULES_HIT:41:355:379:541:800:960:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1431:1437:1515:1516:1518:1534:1541:1593:1594:1711:1730:1747:1777:1792:2393:2559:2562:2828:3138:3139:3140:3141:3142:3353:3865:3866:3867:3874:4321:5007:6261:6742:7808:7903:7904:10004:10400:10848:11026:11232:11473:11658:11914:12043:12438:12517:12519:12555:12740:13069:13311:13357:14196:14394:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: actor33_36067225e591d X-Filterd-Recvd-Size: 2942 Message-ID: <1414531369.10912.14.camel@perches.com> Subject: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 From: Joe Perches To: Jaroslav Kysela , Takashi Iwai Cc: "Wang, Yalin" , Russell King , linux-mm@kvack.org, Will Deacon , Akinobu Mita , linux-arm-kernel@lists.infradead.org, alsa-devel , LKML , linux-mm@kvack.org, Will Deacon , Akinobu Mita , linux-arm-kernel@lists.infradead.org, alsa-devel , LKML Date: Tue, 28 Oct 2014 14:22:49 -0700 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches --- On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > > so that we can use arm/arm64 rbit instruction to do bitrev operation > > by hardware. [] > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h > > index 7ffe03f..ef5b2bb 100644 > > --- a/include/linux/bitrev.h > > +++ b/include/linux/bitrev.h > > @@ -3,6 +3,14 @@ > > > > #include > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > +#include > > + > > +#define bitrev32 __arch_bitrev32 > > +#define bitrev16 __arch_bitrev16 > > +#define bitrev8 __arch_bitrev8 > > + > > +#else > > extern u8 const byte_rev_table[256]; sound/usb/6fire/firmware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c index 3b02e54..62c25e7 100644 --- a/sound/usb/6fire/firmware.c +++ b/sound/usb/6fire/firmware.c @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( while (c != end) { for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++) - buffer[i] = byte_rev_table[(u8) *c]; + buffer[i] = bitrev8((u8)*c); ret = usb6fire_fw_fpga_write(device, buffer, i); if (ret < 0) { From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753751AbaJ2CmI (ORCPT ); Tue, 28 Oct 2014 22:42:08 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:1712 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750858AbaJ2CmF convert rfc822-to-8bit (ORCPT ); Tue, 28 Oct 2014 22:42:05 -0400 From: "Wang, Yalin" To: "'Joe Perches'" , Jaroslav Kysela , Takashi Iwai CC: Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML Date: Wed, 29 Oct 2014 10:42:00 +0800 Subject: RE: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Thread-Topic: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 Thread-Index: Ac/y9VfeDNRCoVSXRyyNvIRV7m0a2AALFzow Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> In-Reply-To: <1414531369.10912.14.camel@perches.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > to eliminate the array. > > Signed-off-by: Joe Perches > --- > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > hardware. > [] > > > diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index > > > 7ffe03f..ef5b2bb 100644 > > > --- a/include/linux/bitrev.h > > > +++ b/include/linux/bitrev.h > > > @@ -3,6 +3,14 @@ > > > > > > #include > > > > > > +#ifdef CONFIG_HAVE_ARCH_BITREVERSE > > > +#include > > > + > > > +#define bitrev32 __arch_bitrev32 > > > +#define bitrev16 __arch_bitrev16 > > > +#define bitrev8 __arch_bitrev8 > > > + > > > +#else > > > extern u8 const byte_rev_table[256]; > > sound/usb/6fire/firmware.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/sound/usb/6fire/firmware.c b/sound/usb/6fire/firmware.c index > 3b02e54..62c25e7 100644 > --- a/sound/usb/6fire/firmware.c > +++ b/sound/usb/6fire/firmware.c > @@ -316,7 +316,7 @@ static int usb6fire_fw_fpga_upload( > > while (c != end) { > for (i = 0; c != end && i < FPGA_BUFSIZE; i++, c++) > - buffer[i] = byte_rev_table[(u8) *c]; > + buffer[i] = bitrev8((u8)*c); > > ret = usb6fire_fw_fpga_write(device, buffer, i); > if (ret < 0) { > I think the most safe way is change byte_rev_table[] to be satic, So that no driver can access it directly, The build error can remind the developer if they use byte_rev_table[] Directly . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755192AbaJ2CwO (ORCPT ); Tue, 28 Oct 2014 22:52:14 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:2453 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755057AbaJ2CwN convert rfc822-to-8bit (ORCPT ); Tue, 28 Oct 2014 22:52:13 -0400 From: "Wang, Yalin" To: "'Will Deacon'" CC: "'Russell King - ARM Linux'" , "'linux-mm@kvack.org'" , "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , "'akinobu.mita@gmail.com'" Date: Wed, 29 Oct 2014 10:52:08 +0800 Subject: RE: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V3] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/yt3RrdcC2TGvVRDGxkId1vLsT0gAa8Naw Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825D@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18259@CNBJMBX05.corpusers.net> <20141027104848.GD8768@arm.com> <35FD53F367049845BC99AC72306C23D103E010D1825A@CNBJMBX05.corpusers.net> <20141028135944.GC29706@arm.com> In-Reply-To: <20141028135944.GC29706@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Will Deacon [mailto:will.deacon@arm.com] > Yup, sorry, I didn't realise this patch covered both architectures. It > would probably be a good idea to split it into 3 parts: a core part, then > the two architectural bits. > > Will Ok , I will split the patch into three parts, And send again . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752531AbaJ2DGT (ORCPT ); Tue, 28 Oct 2014 23:06:19 -0400 Received: from smtprelay0164.hostedemail.com ([216.40.44.164]:59975 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750707AbaJ2DGS (ORCPT ); Tue, 28 Oct 2014 23:06:18 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::::,RULES_HIT:41:355:379:541:599:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1540:1593:1594:1711:1730:1747:1777:1792:2194:2199:2393:2559:2562:2828:2901:3138:3139:3140:3141:3142:3352:3622:3865:3866:3867:3871:3872:3873:3874:4321:5007:6261:6691:7808:10004:10400:10848:11026:11232:11473:11658:11914:12438:12517:12519:12740:13019:13069:13311:13357:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: room48_8e06b969d8738 X-Filterd-Recvd-Size: 2268 Message-ID: <1414551974.10912.16.camel@perches.com> Subject: Re: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 From: Joe Perches To: "Wang, Yalin" Cc: Jaroslav Kysela , Takashi Iwai , Russell King , "linux-mm@kvack.org" , Will Deacon , Akinobu Mita , "linux-arm-kernel@lists.infradead.org" , alsa-devel , LKML Date: Tue, 28 Oct 2014 20:06:14 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <1414531369.10912.14.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825C@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2014-10-29 at 10:42 +0800, Wang, Yalin wrote: > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > > to eliminate the array. [] > > On Sun, 2014-10-26 at 23:46 -0700, Joe Perches wrote: > > > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: > > > > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that > > > > we can use arm/arm64 rbit instruction to do bitrev operation by > > > > hardware. [] > I think the most safe way is change byte_rev_table[] to be satic, > So that no driver can access it directly, > The build error can remind the developer if they use byte_rev_table[] > Directly . You can do that with your later patch, but the existing uses _must_ be converted first so you don't break the build. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752301AbaJ2D21 (ORCPT ); Tue, 28 Oct 2014 23:28:27 -0400 Received: from mail-la0-f52.google.com ([209.85.215.52]:35430 "EHLO mail-la0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750858AbaJ2D20 (ORCPT ); Tue, 28 Oct 2014 23:28:26 -0400 MIME-Version: 1.0 In-Reply-To: <1414392371.8884.2.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> From: Rob Herring Date: Wed, 29 Oct 2014 11:28:04 +0800 Message-ID: Subject: Re: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction To: Joe Perches Cc: "Wang, Yalin" , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 27, 2014 at 2:46 PM, Joe Perches wrote: > On Mon, 2014-10-27 at 14:37 +0800, Wang, Yalin wrote: >> this change add CONFIG_HAVE_ARCH_BITREVERSE config option, >> so that we can use arm/arm64 rbit instruction to do bitrev operation >> by hardware. I don't see the original patch in my inbox, so replying here. >> >> Signed-off-by: Yalin Wang >> --- >> arch/arm/Kconfig | 1 + >> arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ >> include/linux/bitrev.h | 9 +++++++++ >> lib/Kconfig | 9 +++++++++ >> lib/bitrev.c | 2 ++ >> 7 files changed, 64 insertions(+) >> create mode 100644 arch/arm/include/asm/bitrev.h >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index 89c4b5c..426cbcc 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -16,6 +16,7 @@ config ARM >> select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS >> select GENERIC_ALLOCATOR >> select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) >> + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) >> select GENERIC_CLOCKEVENTS_BROADCAST if SMP >> select GENERIC_IDLE_POLL_SETUP >> select GENERIC_IRQ_PROBE [...] >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..263c28c 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -36,6 +36,7 @@ config ARM64 >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> select HAVE_ARCH_JUMP_LABEL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> select HAVE_BPF_JIT The kconfig lists should be sorted. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752602AbaJ2FOY (ORCPT ); Wed, 29 Oct 2014 01:14:24 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:6736 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752223AbaJ2FOW (ORCPT ); Wed, 29 Oct 2014 01:14:22 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , Joe Perches CC: Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" Date: Wed, 29 Oct 2014 13:14:18 +0800 Subject: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQ Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5EXU5032413 this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. We also change byte_rev_table[] to be static, to make sure no drivers can access it directly. Change bitrev16() bitrev32() to be inline function, don't need export symbol for these tiny functions. Signed-off-by: Yalin Wang --- include/linux/bitrev.h | 21 ++++++++++++++++++--- lib/Kconfig | 9 +++++++++ lib/bitrev.c | 19 +++---------------- 3 files changed, 30 insertions(+), 19 deletions(-) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..fa2682c 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,14 +3,29 @@ #include -extern u8 const byte_rev_table[256]; +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 + +#else static inline u8 bitrev8(u8 byte) { return byte_rev_table[byte]; } -extern u16 bitrev16(u16 in); -extern u32 bitrev32(u32 in); +static inline u16 bitrev16(u16 x) +{ + return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); +} + +static inline u32 bitrev32(u32 x) +{ + return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); +} +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..ba13610 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -6,7 +7,7 @@ MODULE_AUTHOR("Akinobu Mita "); MODULE_DESCRIPTION("Bit ordering reversal functions"); MODULE_LICENSE("GPL"); -const u8 byte_rev_table[256] = { +const static u8 byte_rev_table[256] = { 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, @@ -42,18 +43,4 @@ const u8 byte_rev_table[256] = { }; EXPORT_SYMBOL_GPL(byte_rev_table); -u16 bitrev16(u16 x) -{ - return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); -} -EXPORT_SYMBOL(bitrev16); - -/** - * bitrev32 - reverse the order of bits in a u32 value - * @x: value to be bit-reversed - */ -u32 bitrev32(u32 x) -{ - return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); -} -EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753738AbaJ2FPn (ORCPT ); Wed, 29 Oct 2014 01:15:43 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:6763 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751006AbaJ2FPl (ORCPT ); Wed, 29 Oct 2014 01:15:41 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , "'Joe Perches'" CC: "'Russell King - ARM Linux'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Wed, 29 Oct 2014 13:15:38 +0800 Subject: [RFC V4 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V4 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQAAAMGlA= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5Flwe032425 This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..c21a5f4 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754867AbaJ2FRC (ORCPT ); Wed, 29 Oct 2014 01:17:02 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:18346 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750825AbaJ2FRB (ORCPT ); Wed, 29 Oct 2014 01:17:01 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , "'Joe Perches'" CC: "'Russell King - ARM Linux'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Wed, 29 Oct 2014 13:16:52 +0800 Subject: [RFC V4 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V4 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQAAAMGlAAAAxPoA== Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5H7CR032445 This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..b1ec1dd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..292a5de --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM64_BITREV_H +#define __ASM_ARM64_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755248AbaJ2FUV (ORCPT ); Wed, 29 Oct 2014 01:20:21 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:18444 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751165AbaJ2FUU (ORCPT ); Wed, 29 Oct 2014 01:20:20 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , Joe Perches CC: Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" Date: Wed, 29 Oct 2014 13:20:14 +0800 Subject: RE: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V2] arm/arm64:add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQAD4w/w Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18262@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5KSpK032472 > From: Rob Herring [mailto:robherring2@gmail.com] > >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index > >> 9532f8d..263c28c 100644 > >> --- a/arch/arm64/Kconfig > >> +++ b/arch/arm64/Kconfig > >> @@ -36,6 +36,7 @@ config ARM64 > >> select HARDIRQS_SW_RESEND > >> select HAVE_ARCH_AUDITSYSCALL > >> select HAVE_ARCH_JUMP_LABEL > >> + select HAVE_ARCH_BITREVERSE > >> select HAVE_ARCH_KGDB > >> select HAVE_ARCH_TRACEHOOK > >> select HAVE_BPF_JIT > > The kconfig lists should be sorted. > > Rob Got it , Thanks for your remind. {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753094AbaJ2FVm (ORCPT ); Wed, 29 Oct 2014 01:21:42 -0400 Received: from smtprelay0207.hostedemail.com ([216.40.44.207]:43629 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751145AbaJ2FVk (ORCPT ); Wed, 29 Oct 2014 01:21:40 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::,RULES_HIT:41:355:379:541:599:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1538:1593:1594:1711:1714:1730:1747:1777:1792:2393:2559:2562:2828:2901:3138:3139:3140:3141:3142:3351:3622:3865:3866:3867:3872:3873:3874:4321:5007:6120:6261:7903:10004:10400:10848:11026:11232:11473:11658:11914:12114:12438:12517:12519:12740:13069:13311:13357:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: pig46_e541ac98b244 X-Filterd-Recvd-Size: 2047 Message-ID: <1414560096.10912.18.camel@perches.com> Subject: Re: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction From: Joe Perches To: "Wang, Yalin" Cc: "'Rob Herring'" , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" Date: Tue, 28 Oct 2014 22:21:36 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 2014-10-29 at 13:14 +0800, Wang, Yalin wrote: > this change add CONFIG_HAVE_ARCH_BITREVERSE config option, > so that we can use arm/arm64 rbit instruction to do bitrev operation > by hardware. > We also change byte_rev_table[] to be static, > to make sure no drivers can access it directly. You break the build with this patch. You can't do this until the users of the table are converted. So far, they are not. I submitted patches for these uses, but those patches are not yet applied. Please make sure the dependencies for your patches are explicitly stated. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755297AbaJ2Fgf (ORCPT ); Wed, 29 Oct 2014 01:36:35 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:7328 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751165AbaJ2Fge convert rfc822-to-8bit (ORCPT ); Wed, 29 Oct 2014 01:36:34 -0400 From: "Wang, Yalin" To: "'Joe Perches'" CC: "'Rob Herring'" , Russell King - ARM Linux , Will Deacon , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" Date: Wed, 29 Oct 2014 13:36:30 +0800 Subject: RE: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V4 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/zODnQ9lkV+OD2RNWCXe6MjhFHDgAAfPFw Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18263@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <1414560096.10912.18.camel@perches.com> In-Reply-To: <1414560096.10912.18.camel@perches.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Joe Perches [mailto:joe@perches.com] > > We also change byte_rev_table[] to be static, to make sure no drivers > > can access it directly. > > You break the build with this patch. > > You can't do this until the users of the table are converted. > > So far, they are not. > > I submitted patches for these uses, but those patches are not yet applied. > > Please make sure the dependencies for your patches are explicitly stated. > Oh, byte_rev_table[] must be extern, Otherwise, bitrev8() can't access it , I will change it. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753436AbaJ2Fuk (ORCPT ); Wed, 29 Oct 2014 01:50:40 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:7745 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751963AbaJ2Fuj (ORCPT ); Wed, 29 Oct 2014 01:50:39 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , "'Joe Perches'" , "'Russell King - ARM Linux'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Wed, 29 Oct 2014 13:50:35 +0800 Subject: [RFC V5 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V5 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQAAAMGlAAAAxPoAABDRrg Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5ojIg032663 this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use arm/arm64 rbit instruction to do bitrev operation by hardware. Change bitrev16() bitrev32() to be inline function, don't need export symbol for these tiny functions. Signed-off-by: Yalin Wang --- include/linux/bitrev.h | 21 ++++++++++++++++++--- lib/Kconfig | 9 +++++++++ lib/bitrev.c | 17 ++--------------- 3 files changed, 29 insertions(+), 18 deletions(-) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..413c52c 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,14 +3,29 @@ #include -extern u8 const byte_rev_table[256]; +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define bitrev32 __arch_bitrev32 +#define bitrev16 __arch_bitrev16 +#define bitrev8 __arch_bitrev8 +#else +extern u8 const byte_rev_table[256]; static inline u8 bitrev8(u8 byte) { return byte_rev_table[byte]; } -extern u16 bitrev16(u16 in); -extern u32 bitrev32(u32 in); +static inline u16 bitrev16(u16 x) +{ + return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); +} + +static inline u32 bitrev32(u32 x) +{ + return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); +} +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..40ffda9 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -42,18 +43,4 @@ const u8 byte_rev_table[256] = { }; EXPORT_SYMBOL_GPL(byte_rev_table); -u16 bitrev16(u16 x) -{ - return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); -} -EXPORT_SYMBOL(bitrev16); - -/** - * bitrev32 - reverse the order of bits in a u32 value - * @x: value to be bit-reversed - */ -u32 bitrev32(u32 x) -{ - return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); -} -EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755179AbaJ2Fv0 (ORCPT ); Wed, 29 Oct 2014 01:51:26 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:19367 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752972AbaJ2FvZ (ORCPT ); Wed, 29 Oct 2014 01:51:25 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , "'Joe Perches'" , "'Russell King - ARM Linux'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Wed, 29 Oct 2014 13:51:17 +0800 Subject: [RFC V5 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V5 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQAAAMGlAAAAxPoAABDRrgAAArD0A= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5pV6q032667 This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..c21a5f4 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752232AbaJ2FwJ (ORCPT ); Wed, 29 Oct 2014 01:52:09 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:7778 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750712AbaJ2FwH (ORCPT ); Wed, 29 Oct 2014 01:52:07 -0400 From: "Wang, Yalin" To: "'Rob Herring'" , "'Joe Perches'" , "'Russell King - ARM Linux'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Wed, 29 Oct 2014 13:52:00 +0800 Subject: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/zKGffEmlPWtUCT7yIK/xKLtVDxQADp3GQAAAMGlAAAAxPoAABDRrgAAArD0AAAAXfAA== Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id s9T5qEQR032674 This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..b1ec1dd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..292a5de --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,28 @@ +#ifndef __ASM_ARM64_BITREV_H +#define __ASM_ARM64_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + if (__builtin_constant_p(x)) { + x = (x >> 16) | (x << 16); + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); + } + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933497AbaJ3MBe (ORCPT ); Thu, 30 Oct 2014 08:01:34 -0400 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:50886 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932774AbaJ3MBc (ORCPT ); Thu, 30 Oct 2014 08:01:32 -0400 Date: Thu, 30 Oct 2014 12:01:27 +0000 From: Will Deacon To: "Wang, Yalin" Cc: "'Rob Herring'" , "'Joe Perches'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> Thread-Topic: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Accept-Language: en-GB, en-US Content-Language: en-US User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > 2 files changed, 29 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..292a5de > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,28 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > +{ > + if (__builtin_constant_p(x)) { > + x = (x >> 16) | (x << 16); > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); Shouldn't this part be in the generic code? > + } > + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); You can write this more neatly as: asm ("rbit %w0, %w0" : "+r" (x)); Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933673AbaJ3M0q (ORCPT ); Thu, 30 Oct 2014 08:26:46 -0400 Received: from mail-la0-f49.google.com ([209.85.215.49]:45741 "EHLO mail-la0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932947AbaJ3M0o (ORCPT ); Thu, 30 Oct 2014 08:26:44 -0400 MIME-Version: 1.0 In-Reply-To: <20141030120127.GC32589@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> Date: Thu, 30 Oct 2014 13:26:42 +0100 Message-ID: Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction From: Ard Biesheuvel To: Will Deacon Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30 October 2014 13:01, Will Deacon wrote: > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: >> This patch add bitrev.h file to support rbit instruction, >> so that we can do bitrev operation by hardware. >> Signed-off-by: Yalin Wang >> --- >> arch/arm64/Kconfig | 1 + >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 29 insertions(+) >> create mode 100644 arch/arm64/include/asm/bitrev.h >> >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >> index 9532f8d..b1ec1dd 100644 >> --- a/arch/arm64/Kconfig >> +++ b/arch/arm64/Kconfig >> @@ -35,6 +35,7 @@ config ARM64 >> select HANDLE_DOMAIN_IRQ >> select HARDIRQS_SW_RESEND >> select HAVE_ARCH_AUDITSYSCALL >> + select HAVE_ARCH_BITREVERSE >> select HAVE_ARCH_JUMP_LABEL >> select HAVE_ARCH_KGDB >> select HAVE_ARCH_TRACEHOOK >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h >> new file mode 100644 >> index 0000000..292a5de >> --- /dev/null >> +++ b/arch/arm64/include/asm/bitrev.h >> @@ -0,0 +1,28 @@ >> +#ifndef __ASM_ARM64_BITREV_H >> +#define __ASM_ARM64_BITREV_H >> + >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) >> +{ >> + if (__builtin_constant_p(x)) { >> + x = (x >> 16) | (x << 16); >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > Shouldn't this part be in the generic code? > >> + } >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > You can write this more neatly as: > > asm ("rbit %w0, %w0" : "+r" (x)); > This forces GCC to use the same register as input and output, which doesn't necessarily result in the fastest code. (e.g., if the un-bitrev()'ed value is reused again afterwards). On the other hand, the original notation does allow GCC to use the same register, but doesn't force it to, so I prefer the original one. -- Ard. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760175AbaJ3N6D (ORCPT ); Thu, 30 Oct 2014 09:58:03 -0400 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:50944 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759871AbaJ3N6A (ORCPT ); Thu, 30 Oct 2014 09:58:00 -0400 Date: Thu, 30 Oct 2014 13:57:49 +0000 From: Will Deacon To: Ard Biesheuvel Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141030135749.GE32589@arm.com> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 30, 2014 at 12:26:42PM +0000, Ard Biesheuvel wrote: > On 30 October 2014 13:01, Will Deacon wrote: > > On Wed, Oct 29, 2014 at 05:52:00AM +0000, Wang, Yalin wrote: > >> This patch add bitrev.h file to support rbit instruction, > >> so that we can do bitrev operation by hardware. > >> Signed-off-by: Yalin Wang > >> --- > >> arch/arm64/Kconfig | 1 + > >> arch/arm64/include/asm/bitrev.h | 28 ++++++++++++++++++++++++++++ > >> 2 files changed, 29 insertions(+) > >> create mode 100644 arch/arm64/include/asm/bitrev.h > >> > >> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > >> index 9532f8d..b1ec1dd 100644 > >> --- a/arch/arm64/Kconfig > >> +++ b/arch/arm64/Kconfig > >> @@ -35,6 +35,7 @@ config ARM64 > >> select HANDLE_DOMAIN_IRQ > >> select HARDIRQS_SW_RESEND > >> select HAVE_ARCH_AUDITSYSCALL > >> + select HAVE_ARCH_BITREVERSE > >> select HAVE_ARCH_JUMP_LABEL > >> select HAVE_ARCH_KGDB > >> select HAVE_ARCH_TRACEHOOK > >> diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > >> new file mode 100644 > >> index 0000000..292a5de > >> --- /dev/null > >> +++ b/arch/arm64/include/asm/bitrev.h > >> @@ -0,0 +1,28 @@ > >> +#ifndef __ASM_ARM64_BITREV_H > >> +#define __ASM_ARM64_BITREV_H > >> + > >> +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > >> +{ > >> + if (__builtin_constant_p(x)) { > >> + x = (x >> 16) | (x << 16); > >> + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > >> + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > >> + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > >> + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > > > Shouldn't this part be in the generic code? > > > >> + } > >> + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); > > > > You can write this more neatly as: > > > > asm ("rbit %w0, %w0" : "+r" (x)); > > > > This forces GCC to use the same register as input and output, which > doesn't necessarily result in the fastest code. (e.g., if the > un-bitrev()'ed value is reused again afterwards). > On the other hand, the original notation does allow GCC to use the > same register, but doesn't force it to, so I prefer the original one. That's a good point, especially since this is __always_inline. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1161667AbaJaCDd (ORCPT ); Thu, 30 Oct 2014 22:03:33 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:6300 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1161511AbaJaCDc convert rfc822-to-8bit (ORCPT ); Thu, 30 Oct 2014 22:03:32 -0400 From: "Wang, Yalin" To: "'Will Deacon'" CC: "'Rob Herring'" , "'Joe Perches'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 10:03:27 +0800 Subject: RE: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V5 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/0OUvUEsbSUvy4Q6WQKZzfEzbjXgAdXQcQ Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1826F@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18254@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18257@CNBJMBX05.corpusers.net> <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> In-Reply-To: <20141030120127.GC32589@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: Thursday, October 30, 2014 8:01 PM > To: Wang, Yalin > Cc: 'Rob Herring'; 'Joe Perches'; 'Russell King - ARM Linux'; 'linux- > kernel@vger.kernel.org'; 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; > 'linux-arm-kernel@lists.infradead.org' > Subject: Re: [RFC V5 3/3] arm64:add bitrev.h file to support rbit > instruction > > > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) > > +{ > > + if (__builtin_constant_p(x)) { > > + x = (x >> 16) | (x << 16); > > + x = ((x & 0xFF00FF00) >> 8) | ((x & 0x00FF00FF) << 8); > > + x = ((x & 0xF0F0F0F0) >> 4) | ((x & 0x0F0F0F0F) << 4); > > + x = ((x & 0xCCCCCCCC) >> 2) | ((x & 0x33333333) << 2); > > + return ((x & 0xAAAAAAAA) >> 1) | ((x & 0x55555555) << 1); > > Shouldn't this part be in the generic code? Good idea, I will change this part into linux/bitrev.h . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758655AbaJaFkZ (ORCPT ); Fri, 31 Oct 2014 01:40:25 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:5733 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752856AbaJaFkY convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 01:40:24 -0400 From: "Wang, Yalin" To: "'Will Deacon'" , Ard Biesheuvel CC: Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Date: Fri, 31 Oct 2014 13:40:20 +0800 Subject: [RFC V6 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V6 1/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/Q Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> In-Reply-To: <20141030135749.GE32589@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org this change add CONFIG_HAVE_ARCH_BITREVERSE config option, so that we can use some architecture's bitrev hardware instruction to do bitrev operation. Introduce __constant_bitrev* macro for constant bitrev operation. Change __bitrev16() __bitrev32() to be inline function, don't need export symbol for these tiny functions. Signed-off-by: Yalin Wang --- include/linux/bitrev.h | 77 +++++++++++++++++++++++++++++++++++++++++++++++--- lib/Kconfig | 9 ++++++ lib/bitrev.c | 17 ++--------- 3 files changed, 84 insertions(+), 19 deletions(-) diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index 7ffe03f..fb790b8 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -3,14 +3,83 @@ #include -extern u8 const byte_rev_table[256]; +#ifdef CONFIG_HAVE_ARCH_BITREVERSE +#include + +#define __bitrev32 __arch_bitrev32 +#define __bitrev16 __arch_bitrev16 +#define __bitrev8 __arch_bitrev8 -static inline u8 bitrev8(u8 byte) +#else +extern u8 const byte_rev_table[256]; +static inline u8 __bitrev8(u8 byte) { return byte_rev_table[byte]; } -extern u16 bitrev16(u16 in); -extern u32 bitrev32(u32 in); +static inline u16 __bitrev16(u16 x) +{ + return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8); +} + +static inline u32 __bitrev32(u32 x) +{ + return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16); +} + +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ + +#define __constant_bitrev32(x) \ +({ \ + u32 __x = x; \ + __x = (__x >> 16) | (__x << 16); \ + __x = ((__x & (u32)0xFF00FF00UL) >> 8) | ((__x & (u32)0x00FF00FFUL) << 8); \ + __x = ((__x & (u32)0xF0F0F0F0UL) >> 4) | ((__x & (u32)0x0F0F0F0FUL) << 4); \ + __x = ((__x & (u32)0xCCCCCCCCUL) >> 2) | ((__x & (u32)0x33333333UL) << 2); \ + __x = ((__x & (u32)0xAAAAAAAAUL) >> 1) | ((__x & (u32)0x55555555UL) << 1); \ + __x; \ +}) + +#define __constant_bitrev16(x) \ +({ \ + u16 __x = x; \ + __x = (__x >> 8) | (__x << 8); \ + __x = ((__x & (u16)0xF0F0U) >> 4) | ((__x & (u16)0x0F0FU) << 4); \ + __x = ((__x & (u16)0xCCCCU) >> 2) | ((__x & (u16)0x3333U) << 2); \ + __x = ((__x & (u16)0xAAAAU) >> 1) | ((__x & (u16)0x5555U) << 1); \ + __x; \ +}) + +#define __constant_bitrev8(x) \ +({ \ + u8 __x = x; \ + __x = (__x >> 4) | (__x << 4); \ + __x = ((__x & (u8)0xCCU) >> 2) | ((__x & (u8)0x33U) << 2); \ + __x = ((__x & (u8)0xAAU) >> 1) | ((__x & (u8)0x55U) << 1); \ + __x; \ +}) + +#define bitrev32(x) \ +({ \ + u32 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev32(__x) : \ + __bitrev32(__x); \ +}) + +#define bitrev16(x) \ +({ \ + u16 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev16(__x) : \ + __bitrev16(__x); \ + }) +#define bitrev8(x) \ +({ \ + u8 __x = x; \ + __builtin_constant_p(__x) ? \ + __constant_bitrev8(__x) : \ + __bitrev8(__x) ; \ + }) #endif /* _LINUX_BITREV_H */ diff --git a/lib/Kconfig b/lib/Kconfig index 54cf309..cd177ca 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -13,6 +13,15 @@ config RAID6_PQ config BITREVERSE tristate +config HAVE_ARCH_BITREVERSE + boolean + default n + depends on BITREVERSE + help + This option provides an config for the architecture which have instruction + can do bitreverse operation, we use the hardware instruction if the architecture + have this capability. + config RATIONAL boolean diff --git a/lib/bitrev.c b/lib/bitrev.c index 3956203..40ffda9 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,3 +1,4 @@ +#ifndef CONFIG_HAVE_ARCH_BITREVERSE #include #include #include @@ -42,18 +43,4 @@ const u8 byte_rev_table[256] = { }; EXPORT_SYMBOL_GPL(byte_rev_table); -u16 bitrev16(u16 x) -{ - return (bitrev8(x & 0xff) << 8) | bitrev8(x >> 8); -} -EXPORT_SYMBOL(bitrev16); - -/** - * bitrev32 - reverse the order of bits in a u32 value - * @x: value to be bit-reversed - */ -u32 bitrev32(u32 x) -{ - return (bitrev16(x & 0xffff) << 16) | bitrev16(x >> 16); -} -EXPORT_SYMBOL(bitrev32); +#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759287AbaJaFlA (ORCPT ); Fri, 31 Oct 2014 01:41:00 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:13777 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752634AbaJaFk7 convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 01:40:59 -0400 From: "Wang, Yalin" To: "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" CC: "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 13:40:55 +0800 Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/QAARlW3A= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..e9b2571 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759493AbaJaFlx (ORCPT ); Fri, 31 Oct 2014 01:41:53 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:5776 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753002AbaJaFlw convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 01:41:52 -0400 From: "Wang, Yalin" To: "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" CC: "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 13:41:48 +0800 Subject: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/QAARpyNA= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm64/include/asm/bitrev.h diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9532f8d..b1ec1dd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -35,6 +35,7 @@ config ARM64 select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_BITREVERSE select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB select HAVE_ARCH_TRACEHOOK diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h new file mode 100644 index 0000000..706a209 --- /dev/null +++ b/arch/arm64/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM64_BITREV_H +#define __ASM_ARM64_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %w0, %w1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759590AbaJaFmx (ORCPT ); Fri, 31 Oct 2014 01:42:53 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:5810 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753058AbaJaFmw convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 01:42:52 -0400 From: "Wang, Yalin" To: "'Will Deacon'" , "'Ard Biesheuvel'" CC: "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 13:42:44 +0800 Subject: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/QAARlW3AAAA1OUA== Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add bitrev.h file to support rbit instruction, so that we can do bitrev operation by hardware. Signed-off-by: Yalin Wang --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 arch/arm/include/asm/bitrev.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -28,6 +28,7 @@ config ARM select HANDLE_DOMAIN_IRQ select HARDIRQS_SW_RESEND select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file mode 100644 index 0000000..e9b2571 --- /dev/null +++ b/arch/arm/include/asm/bitrev.h @@ -0,0 +1,21 @@ +#ifndef __ASM_ARM_BITREV_H +#define __ASM_ARM_BITREV_H + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); + return x; +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32((u32)x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + return __arch_bitrev32((u32)x) >> 24; +} + +#endif + -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751588AbaJaHkv (ORCPT ); Fri, 31 Oct 2014 03:40:51 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:9758 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750710AbaJaHkt convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 03:40:49 -0400 From: "Wang, Yalin" To: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 15:40:46 +0800 Subject: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Topic: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/QAARlW3AAAA1OUAAEHhFg Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), because uprobe_notify_resume() have do this. Signed-off-by: Yalin Wang --- arch/arm/kernel/signal.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index bd19834..ff598f0 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) return restart; } syscall = 0; - } else if (thread_flags & _TIF_UPROBE) { - clear_thread_flag(TIF_UPROBE); + } else if (thread_flags & _TIF_UPROBE) uprobe_notify_resume(regs); - } else { + else { clear_thread_flag(TIF_NOTIFY_RESUME); tracehook_notify_resume(regs); } -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751631AbaJaHpk (ORCPT ); Fri, 31 Oct 2014 03:45:40 -0400 Received: from smtprelay0126.hostedemail.com ([216.40.44.126]:41096 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750742AbaJaHpj (ORCPT ); Fri, 31 Oct 2014 03:45:39 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::,RULES_HIT:41:355:379:541:599:968:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1515:1516:1518:1534:1539:1593:1594:1711:1714:1730:1747:1777:1792:2393:2559:2562:2828:3138:3139:3140:3141:3142:3351:3622:3865:3870:4321:5007:6261:10004:10400:10848:11026:11232:11473:11658:11914:12043:12114:12296:12438:12517:12519:12740:13069:13311:13357:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: kite40_4e1c11dfdda4a X-Filterd-Recvd-Size: 2824 Message-ID: <1414741535.8928.2.camel@perches.com> Subject: Re: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) From: Joe Perches To: "Wang, Yalin" Cc: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 00:45:35 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2014-10-31 at 15:40 +0800, Wang, Yalin wrote: > This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), > because uprobe_notify_resume() have do this. [] > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c [] > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) > return restart; > } > syscall = 0; > - } else if (thread_flags & _TIF_UPROBE) { > - clear_thread_flag(TIF_UPROBE); > + } else if (thread_flags & _TIF_UPROBE) > uprobe_notify_resume(regs); > - } else { > + else { > clear_thread_flag(TIF_NOTIFY_RESUME); > tracehook_notify_resume(regs); > } Please keep the braces. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756824AbaJaHvs (ORCPT ); Fri, 31 Oct 2014 03:51:48 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:10155 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756681AbaJaHvo convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 03:51:44 -0400 From: "Wang, Yalin" To: "'Joe Perches'" CC: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 15:51:41 +0800 Subject: RE: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Topic: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Index: Ac/03rMWWFkGX/cdRK6lX5CjAvaTsAAALaeg Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> In-Reply-To: <1414741535.8928.2.camel@perches.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Joe Perches [mailto:joe@perches.com] > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > [] > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > thread_flags, int syscall) > > return restart; > > } > > syscall = 0; > > - } else if (thread_flags & _TIF_UPROBE) { > > - clear_thread_flag(TIF_UPROBE); > > + } else if (thread_flags & _TIF_UPROBE) > > uprobe_notify_resume(regs); > > - } else { > > + else { > > clear_thread_flag(TIF_NOTIFY_RESUME); > > tracehook_notify_resume(regs); > > } > > Please keep the braces. mm.. could I know the reason ? :) Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755728AbaJaHyY (ORCPT ); Fri, 31 Oct 2014 03:54:24 -0400 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:18270 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751212AbaJaHyX convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 03:54:23 -0400 From: "Wang, Yalin" To: "'Will Deacon'" , "'Ard Biesheuvel'" CC: "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 15:54:16 +0800 Subject: RE: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Topic: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit instruction Thread-Index: Ac/0SYsLYyTdMNPAS1SmHcF7f8oZ+gAcg3/QAARlW3AABKQ3AA== Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827D@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Wang, Yalin > Subject: [RFC V6 2/3] add CONFIG_HAVE_ARCH_BITREVERSE to support rbit > instruction > > This patch add bitrev.h file to support rbit instruction, so that we can do > bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 89c4b5c..be92b3b > 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) diff --git > a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h new file > mode 100644 index 0000000..e9b2571 > --- /dev/null > +++ b/arch/arm/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM_BITREV_H > +#define __ASM_ARM_BITREV_H > + > +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) { > + __asm__ ("rbit %0, %1" : "=r" (x) : "r" (x)); > + return x; > +} > + > +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) { > + return __arch_bitrev32((u32)x) >> 16; > +} > + > +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) { > + return __arch_bitrev32((u32)x) >> 24; > +} > + > +#endif > + > -- > 2.1.1 Wrong title, please ignore this one , I have resend another [RFC V6 2/3] . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755961AbaJaH6P (ORCPT ); Fri, 31 Oct 2014 03:58:15 -0400 Received: from smtprelay0140.hostedemail.com ([216.40.44.140]:39380 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750797AbaJaH6N (ORCPT ); Fri, 31 Oct 2014 03:58:13 -0400 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 2,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::,RULES_HIT:41:355:379:541:599:800:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1540:1593:1594:1711:1730:1747:1777:1792:2393:2559:2562:2828:3138:3139:3140:3141:3142:3352:3622:3865:3868:3870:4321:5007:6119:6261:7576:8531:8957:10004:10400:10848:11026:11473:11658:11914:12043:12114:12296:12438:12517:12519:12740:13069:13311:13357:14096:14097:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: gate45_2a585a47ec726 X-Filterd-Recvd-Size: 3166 Message-ID: <1414742289.8928.5.camel@perches.com> Subject: Re: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) From: Joe Perches To: "Wang, Yalin" Cc: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 00:58:09 -0700 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2014-10-31 at 15:51 +0800, Wang, Yalin wrote: > > From: Joe Perches [mailto:joe@perches.com] > > > diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c > > [] > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned int > > thread_flags, int syscall) > > > return restart; > > > } > > > syscall = 0; > > > - } else if (thread_flags & _TIF_UPROBE) { > > > - clear_thread_flag(TIF_UPROBE); > > > + } else if (thread_flags & _TIF_UPROBE) > > > uprobe_notify_resume(regs); > > > - } else { > > > + else { > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > tracehook_notify_resume(regs); > > > } > > > > Please keep the braces. > > mm.. could I know the reason ? :) Try read Documentation/CodingStyle Chapter 3: Placing Braces and Spaces use braces in both branches: if (condition) { do_this(); do_that(); } else { otherwise(); } From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756421AbaJaIBU (ORCPT ); Fri, 31 Oct 2014 04:01:20 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:10457 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750935AbaJaIBT convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 04:01:19 -0400 From: "Wang, Yalin" To: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 16:01:13 +0800 Subject: [RFC V2] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Topic: [RFC V2] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Index: Ac/03rMWWFkGX/cdRK6lX5CjAvaTsAAALaegAABTt7A= Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827F@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch remove clear_thread_flag(TIF_UPROBE) in do_work_pending(), because uprobe_notify_resume() have do this. Signed-off-by: Yalin Wang --- arch/arm/kernel/signal.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index bd19834..8aa6f1b 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c @@ -592,7 +592,6 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall) } syscall = 0; } else if (thread_flags & _TIF_UPROBE) { - clear_thread_flag(TIF_UPROBE); uprobe_notify_resume(regs); } else { clear_thread_flag(TIF_NOTIFY_RESUME); -- 2.1.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754551AbaJaH7m (ORCPT ); Fri, 31 Oct 2014 03:59:42 -0400 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:10421 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750817AbaJaH7l convert rfc822-to-8bit (ORCPT ); Fri, 31 Oct 2014 03:59:41 -0400 From: "Wang, Yalin" To: "'Joe Perches'" CC: "'Will Deacon'" , "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 31 Oct 2014 15:59:37 +0800 Subject: RE: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Topic: [RFC] arm:remove clear_thread_flag(TIF_UPROBE) Thread-Index: Ac/04G2Oik0iMWuUSRi4S5gJBTWE9AAAB5BA Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1827E@CNBJMBX05.corpusers.net> References: <1414392371.8884.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1825F@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D1827B@CNBJMBX05.corpusers.net> <1414741535.8928.2.camel@perches.com> <35FD53F367049845BC99AC72306C23D103E010D1827C@CNBJMBX05.corpusers.net> <1414742289.8928.5.camel@perches.com> In-Reply-To: <1414742289.8928.5.camel@perches.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Joe Perches [mailto:joe@perches.com] > > > > @@ -591,10 +591,9 @@ do_work_pending(struct pt_regs *regs, unsigned > int > > > thread_flags, int syscall) > > > > return restart; > > > > } > > > > syscall = 0; > > > > - } else if (thread_flags & _TIF_UPROBE) { > > > > - clear_thread_flag(TIF_UPROBE); > > > > + } else if (thread_flags & _TIF_UPROBE) > > > > uprobe_notify_resume(regs); > > > > - } else { > > > > + else { > > > > clear_thread_flag(TIF_NOTIFY_RESUME); > > > > tracehook_notify_resume(regs); > > > > } > > > > > > Please keep the braces. > > > > mm.. could I know the reason ? :) > > Try read Documentation/CodingStyle > > Chapter 3: Placing Braces and Spaces > > use braces in both branches: > > if (condition) { > do_this(); > do_that(); > } else { > otherwise(); > } > Got it, I will resend one . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758568AbaJaKnN (ORCPT ); Fri, 31 Oct 2014 06:43:13 -0400 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:51398 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756380AbaJaKnM (ORCPT ); Fri, 31 Oct 2014 06:43:12 -0400 Date: Fri, 31 Oct 2014 10:43:06 +0000 From: Will Deacon To: "Wang, Yalin" Cc: "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141031104305.GC6731@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 31, 2014 at 05:41:48AM +0000, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm64/include/asm/bitrev.h > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 9532f8d..b1ec1dd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -35,6 +35,7 @@ config ARM64 > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL > + select HAVE_ARCH_BITREVERSE > select HAVE_ARCH_JUMP_LABEL > select HAVE_ARCH_KGDB > select HAVE_ARCH_TRACEHOOK > diff --git a/arch/arm64/include/asm/bitrev.h b/arch/arm64/include/asm/bitrev.h > new file mode 100644 > index 0000000..706a209 > --- /dev/null > +++ b/arch/arm64/include/asm/bitrev.h > @@ -0,0 +1,21 @@ > +#ifndef __ASM_ARM64_BITREV_H > +#define __ASM_ARM64_BITREV_H Really minor nit, but we don't tend to include 'ARM64' in our header guards, so this should just be __ASM_BITREV_H. With that change, Acked-by: Will Deacon Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752910AbaKCCRZ (ORCPT ); Sun, 2 Nov 2014 21:17:25 -0500 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:2702 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752138AbaKCCRX convert rfc822-to-8bit (ORCPT ); Sun, 2 Nov 2014 21:17:23 -0500 From: "Wang, Yalin" To: "'Will Deacon'" CC: "'Ard Biesheuvel'" , "'Russell King - ARM Linux'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Mon, 3 Nov 2014 10:17:15 +0800 Subject: RE: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/093pf+266lKYFRgKWSwcrgci7HgCFELlg Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> In-Reply-To: <20141031104305.GC6731@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Will Deacon [mailto:will.deacon@arm.com] > > +#ifndef __ASM_ARM64_BITREV_H > > +#define __ASM_ARM64_BITREV_H > > Really minor nit, but we don't tend to include 'ARM64' in our header guards, > so this should just be __ASM_BITREV_H. > > With that change, > > Acked-by: Will Deacon > I have send the patch to the patch system: http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 8187/1 8188/1 8189/1 Just remind you that , should also cherry-pick Joe Perches's 2 patches: [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 To make sure there is no build error when build these 2 drivers. Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752042AbaKCIrh (ORCPT ); Mon, 3 Nov 2014 03:47:37 -0500 Received: from mail-la0-f54.google.com ([209.85.215.54]:48624 "EHLO mail-la0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751435AbaKCIre (ORCPT ); Mon, 3 Nov 2014 03:47:34 -0500 MIME-Version: 1.0 In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18260@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> Date: Mon, 3 Nov 2014 09:47:32 +0100 Message-ID: Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction From: Ard Biesheuvel To: "Wang, Yalin" Cc: Will Deacon , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 3 November 2014 03:17, Wang, Yalin wrote: >> From: Will Deacon [mailto:will.deacon@arm.com] >> > +#ifndef __ASM_ARM64_BITREV_H >> > +#define __ASM_ARM64_BITREV_H >> >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, >> so this should just be __ASM_BITREV_H. >> >> With that change, >> >> Acked-by: Will Deacon >> > I have send the patch to the patch system: > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > 8187/1 8188/1 8189/1 > > Just remind you that , should also cherry-pick Joe Perches's > 2 patches: > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > To make sure there is no build error when build these 2 drivers. > If this is the case, I suggest you update patch 8187/1 to retain the byte_rev_table symbol, even in the accelerated case, and remove it with a followup patch once Joe's patches have landed upstream. Also, a link to the patches would be nice, and perhaps a bit of explanation how/when they are expected to be merged. -- Ard. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751964AbaKCJvC (ORCPT ); Mon, 3 Nov 2014 04:51:02 -0500 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:51974 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751804AbaKCJu6 (ORCPT ); Mon, 3 Nov 2014 04:50:58 -0500 Date: Mon, 3 Nov 2014 09:50:51 +0000 From: Will Deacon To: Ard Biesheuvel Cc: "Wang, Yalin" , Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Message-ID: <20141103095051.GA23019@arm.com> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 03, 2014 at 08:47:32AM +0000, Ard Biesheuvel wrote: > On 3 November 2014 03:17, Wang, Yalin wrote: > >> From: Will Deacon [mailto:will.deacon@arm.com] > >> > +#ifndef __ASM_ARM64_BITREV_H > >> > +#define __ASM_ARM64_BITREV_H > >> > >> Really minor nit, but we don't tend to include 'ARM64' in our header guards, > >> so this should just be __ASM_BITREV_H. > >> > >> With that change, > >> > >> Acked-by: Will Deacon > >> > > I have send the patch to the patch system: > > http://www.arm.linux.org.uk/developer/patches/search.php?uid=4025 > > > > 8187/1 8188/1 8189/1 > > > > Just remind you that , should also cherry-pick Joe Perches's > > 2 patches: > > [PATCH] 6fire: Convert byte_rev_table uses to bitrev8 > > [PATCH] carl9170: Convert byte_rev_table uses to bitrev8 > > > > To make sure there is no build error when build these 2 drivers. > > > > If this is the case, I suggest you update patch 8187/1 to retain the > byte_rev_table symbol, even in the accelerated case, and remove it > with a followup patch once Joe's patches have landed upstream. Also, a > link to the patches would be nice, and perhaps a bit of explanation > how/when they are expected to be merged. Indeed, or instead put together a series with the appropriate acks so somebody can merge it all in one go. Merging this on a piecemeal basis is going to cause breakages (as you pointed out). Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751605AbaKDBps (ORCPT ); Mon, 3 Nov 2014 20:45:48 -0500 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:12338 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751046AbaKDBpr convert rfc822-to-8bit (ORCPT ); Mon, 3 Nov 2014 20:45:47 -0500 From: "Wang, Yalin" To: "'Will Deacon'" , Ard Biesheuvel CC: Russell King - ARM Linux , "linux-kernel@vger.kernel.org" , "akinobu.mita@gmail.com" , "linux-mm@kvack.org" , Joe Perches , "linux-arm-kernel@lists.infradead.org" Date: Tue, 4 Nov 2014 09:45:42 +0800 Subject: RE: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 3/3] arm64:add bitrev.h file to support rbit instruction Thread-Index: Ac/3S6wTI0zxMshrQ4qGSbsKS1fzQAAhTWMw Message-ID: <35FD53F367049845BC99AC72306C23D103E010D18288@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18274@CNBJMBX05.corpusers.net> <20141031104305.GC6731@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18287@CNBJMBX05.corpusers.net> <20141103095051.GA23019@arm.com> In-Reply-To: <20141103095051.GA23019@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Will Deacon [mailto:will.deacon@arm.com] > > > > If this is the case, I suggest you update patch 8187/1 to retain the > > byte_rev_table symbol, even in the accelerated case, and remove it > > with a followup patch once Joe's patches have landed upstream. Also, a > > link to the patches would be nice, and perhaps a bit of explanation > > how/when they are expected to be merged. > > Indeed, or instead put together a series with the appropriate acks so > somebody can merge it all in one go. Merging this on a piecemeal basis is > going to cause breakages (as you pointed out). > > Will Hi Will, Could I add you as ack-by , and submit these 2 patches into the Patch system ? So you can merge them together . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934854AbaKMXxg (ORCPT ); Thu, 13 Nov 2014 18:53:36 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:38847 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934400AbaKMXxe (ORCPT ); Thu, 13 Nov 2014 18:53:34 -0500 Date: Thu, 13 Nov 2014 23:53:22 +0000 From: Russell King - ARM Linux To: "Wang, Yalin" Cc: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > This patch add bitrev.h file to support rbit instruction, > so that we can do bitrev operation by hardware. > Signed-off-by: Yalin Wang > --- > arch/arm/Kconfig | 1 + > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > 2 files changed, 22 insertions(+) > create mode 100644 arch/arm/include/asm/bitrev.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 89c4b5c..be92b3b 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -28,6 +28,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) Looking at this, this is just wrong. Take a moment to consider what happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. What happens if an ARMv6 CPU tries to execute an rbit instruction? Second point (which isn't obvious from your submissions on-list) is that you've loaded the patch system up with patches for other parts of the kernel tree for which I am not responsible for. As such, I can't take those patches without the sub-tree maintainer acking them. Also, the commit text in those patches look weird: 6fire: Convert byte_rev_table uses to bitrev8 Use the inline function instead of directly indexing the array. This allows some architectures with hardware instructions for bit reversals to eliminate the array. Signed-off-by: Joe Perches <(address hidden)> Signed-off-by: Yalin Wang <(address hidden)> Why is Joe signing off on these patches? As his is the first sign-off, one assumes that he was responsible for creating the patch in the first place, but there is no From: line marking him as the author. Shouldn't his entry be an Acked-by: ? Confused. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964834AbaKNAFf (ORCPT ); Thu, 13 Nov 2014 19:05:35 -0500 Received: from smtprelay0075.hostedemail.com ([216.40.44.75]:51308 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933846AbaKNAFe (ORCPT ); Thu, 13 Nov 2014 19:05:34 -0500 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 50,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::,RULES_HIT:41:355:379:541:599:800:960:967:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1542:1593:1594:1711:1730:1747:1777:1792:2393:2525:2553:2560:2563:2682:2685:2693:2828:2859:2933:2937:2939:2942:2945:2947:2951:2954:3022:3138:3139:3140:3141:3142:3354:3622:3865:3866:3867:3870:3871:3872:3873:3874:3934:3936:3938:3941:3944:3947:3950:3953:3956:3959:4321:4605:4641:5007:6119:6120:6261:6691:7808:7903:8985:9010:9025:10004:10400:10848:11026:11232:11473:11658:11914:12043:12050:12291:12438:12517:12519:12555:12663:12740:13161:13229:14096:14097:21060:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: fuel96_4d588d279424b X-Filterd-Recvd-Size: 4132 Message-ID: <1415923530.4223.17.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches To: Russell King - ARM Linux , Takashi Iwai Cc: "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Thu, 13 Nov 2014 16:05:30 -0800 In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, > > so that we can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: > > 6fire: Convert byte_rev_table uses to bitrev8 > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit > reversals to eliminate the array. > > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> > > Why is Joe signing off on these patches? > Shouldn't his entry be an Acked-by: ? I didn't sign off on or ack the "add bitrev.h" patch. I created 2 patches that converted direct uses of byte_rev_table to that bitrev8 static inline. One of them is already in -next 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 The other hasn't been applied. https://lkml.org/lkml/2014/10/28/1056 Maybe Takashi Iwai will get around to it one day. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754225AbaKNARg (ORCPT ); Thu, 13 Nov 2014 19:17:36 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:38879 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753163AbaKNARe (ORCPT ); Thu, 13 Nov 2014 19:17:34 -0500 Date: Fri, 14 Nov 2014 00:17:21 +0000 From: Russell King - ARM Linux To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114001720.GD4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415923530.4223.17.camel@perches.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. Correct, I never said you did. Please read my message a bit more carefully next time, huh? > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. Great, so I can just discard these that were incorrectly submitted to me then. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964823AbaKNApt (ORCPT ); Thu, 13 Nov 2014 19:45:49 -0500 Received: from smtprelay0020.hostedemail.com ([216.40.44.20]:42400 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933889AbaKNApr (ORCPT ); Thu, 13 Nov 2014 19:45:47 -0500 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 50,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::,RULES_HIT:41:355:379:541:599:800:960:967:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1535:1543:1593:1594:1605:1711:1730:1747:1777:1792:2110:2393:2525:2553:2560:2563:2682:2685:2693:2828:2859:2895:2933:2937:2939:2942:2945:2947:2951:2954:3022:3138:3139:3140:3141:3142:3622:3865:3866:3867:3868:3870:3871:3872:3873:3874:3934:3936:3938:3941:3944:3947:3950:3953:3956:3959:4321:4384:4605:4641:5007:6119:6120:6248:6261:6691:7808:7903:9010:9025:10004:10226:10400:10848:11026:11232:11473:11658:11914:12043:12050:12214:12291:12438:12517:12519:12555:12663:12740:13095:14096:14097:21060:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: steel64_898ae260b7222 X-Filterd-Recvd-Size: 5030 Message-ID: <1415925943.4141.1.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches To: Russell King - ARM Linux Cc: Takashi Iwai , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Thu, 13 Nov 2014 16:45:43 -0800 In-Reply-To: <20141114001720.GD4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > Correct, I never said you did. Please read my message a bit more carefully > next time, huh? You've no reason to write that Russell. I'm not trying to be anything other than clear and no I didn't say you said that either. Why not make your own writing clearer or your own memory sharper then eh? Reply on the patch I actually wrote. You were cc'd on it when I submitted it. > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > Great, so I can just discard these that were incorrectly submitted to me > then. I think you shouldn't apply these patches or updated ones either until all the current uses are converted. cheers, Joe From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965162AbaKNBSw (ORCPT ); Thu, 13 Nov 2014 20:18:52 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:38941 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S934547AbaKNBSt (ORCPT ); Thu, 13 Nov 2014 20:18:49 -0500 Date: Fri, 14 Nov 2014 01:18:32 +0000 From: Russell King - ARM Linux To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114011832.GE4042@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415925943.4141.1.camel@perches.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 00:17 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:05:30PM -0800, Joe Perches wrote: > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > Correct, I never said you did. Please read my message a bit more carefully > > next time, huh? > > You've no reason to write that Russell. Absolutely I have, but I'm not going to discuss it because I'll just end up flaming you because in my mind you are the one who is completely mistaken with your comments. In case it hasn't been realised, I hardly read this mailing list anymore, or messages that I'm Cc'd on. I do read most messages that I'm in the To: line, but generally not if they're DT changes (which always end up being marked To: me.) > > Great, so I can just discard these that were incorrectly submitted to me > > then. > > I think you shouldn't apply these patches or updated > ones either until all the current uses are converted. Where are the dependencies mentioned? How do I get to know when all the dependencies are met? Who is tracking the dependencies? -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934890AbaKNB0t (ORCPT ); Thu, 13 Nov 2014 20:26:49 -0500 Received: from smtprelay0107.hostedemail.com ([216.40.44.107]:46135 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933754AbaKNB0s (ORCPT ); Thu, 13 Nov 2014 20:26:48 -0500 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 50,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::,RULES_HIT:41:355:379:541:599:967:973:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1538:1593:1594:1711:1714:1730:1747:1777:1792:2393:2525:2553:2560:2563:2682:2685:2828:2859:2895:2933:2937:2939:2942:2945:2947:2951:2954:3022:3138:3139:3140:3141:3142:3351:3622:3865:3867:3871:3872:3873:3934:3936:3938:3941:3944:3947:3950:3953:3956:3959:4321:5007:6120:6261:8985:9025:10004:10400:10848:11232:11658:11914:12043:12517:12519:12740:13069:13311:13357:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: bikes60_398ad83fb041f X-Filterd-Recvd-Size: 2272 Message-ID: <1415928394.4141.3.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches To: Russell King - ARM Linux Cc: Takashi Iwai , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Thu, 13 Nov 2014 17:26:34 -0800 In-Reply-To: <20141114011832.GE4042@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > I think you shouldn't apply these patches or updated > > ones either until all the current uses are converted. > > Where are the dependencies mentioned? I mentioned it when these patches (which are not mine btw), were submitted the second time. https://lkml.org/lkml/2014/10/27/69 > How do I get to know when all > the dependencies are met? No idea. > Who is tracking the dependencies? Not me. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934964AbaKNCBj (ORCPT ); Thu, 13 Nov 2014 21:01:39 -0500 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:12020 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933518AbaKNCBi convert rfc822-to-8bit (ORCPT ); Thu, 13 Nov 2014 21:01:38 -0500 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" CC: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 14 Nov 2014 10:01:34 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: Ac//nQoUxyiR4A/+S1KTxThngzC6WQAET/GA Message-ID: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> In-Reply-To: <20141113235322.GC4042@n2100.arm.linux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, November 14, 2014 7:53 AM > To: Wang, Yalin > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > This patch add bitrev.h file to support rbit instruction, so that we > > can do bitrev operation by hardware. > > Signed-off-by: Yalin Wang > > --- > > arch/arm/Kconfig | 1 + > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > 2 files changed, 22 insertions(+) > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 89c4b5c..be92b3b 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -28,6 +28,7 @@ config ARM > > select HANDLE_DOMAIN_IRQ > > select HARDIRQS_SW_RESEND > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > Looking at this, this is just wrong. Take a moment to consider what > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > What happens if an ARMv6 CPU tries to execute an rbit instruction? Is it possible to build a kernel that support both CPU_V6 and CPU_V7? I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? If there is problem like you said, How about this solution: select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > Second point (which isn't obvious from your submissions on-list) is that > you've loaded the patch system up with patches for other parts of the > kernel tree for which I am not responsible for. As such, I can't take > those patches without the sub-tree maintainer acking them. Also, the > commit text in those patches look weird: > > 6fire: Convert byte_rev_table uses to bitrev8 > > Use the inline function instead of directly indexing the array. > > This allows some architectures with hardware instructions for bit reversals > to eliminate the array. > > Signed-off-by: Joe Perches <(address hidden)> > Signed-off-by: Yalin Wang <(address hidden)> > > Why is Joe signing off on these patches? As his is the first sign-off, one > assumes that he was responsible for creating the patch in the first place, > but there is no From: line marking him as the author. Shouldn't his entry > be an Acked-by: ? > > Confused. For this patch, I just cherry-pick from Joe, If you are not responsible for this part, I will submit to the maintainers for these patches . Sorry for that . From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754379AbaKNGhS (ORCPT ); Fri, 14 Nov 2014 01:37:18 -0500 Received: from cantor2.suse.de ([195.135.220.15]:52577 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754291AbaKNGhP (ORCPT ); Fri, 14 Nov 2014 01:37:15 -0500 Date: Fri, 14 Nov 2014 07:37:13 +0100 Message-ID: From: Takashi Iwai To: Joe Perches Cc: Russell King - ARM Linux , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415923530.4223.17.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/24.4 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org At Thu, 13 Nov 2014 16:05:30 -0800, Joe Perches wrote: > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, > > > so that we can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > Second point (which isn't obvious from your submissions on-list) is that > > you've loaded the patch system up with patches for other parts of the > > kernel tree for which I am not responsible for. As such, I can't take > > those patches without the sub-tree maintainer acking them. Also, the > > commit text in those patches look weird: > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > Use the inline function instead of directly indexing the array. > > > > This allows some architectures with hardware instructions for bit > > reversals to eliminate the array. > > > > Signed-off-by: Joe Perches <(address hidden)> > > Signed-off-by: Yalin Wang <(address hidden)> > > > > Why is Joe signing off on these patches? > > Shouldn't his entry be an Acked-by: ? > > I didn't sign off on or ack the "add bitrev.h" patch. > > I created 2 patches that converted direct uses of byte_rev_table > to that bitrev8 static inline. One of them is already in -next > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > The other hasn't been applied. > > https://lkml.org/lkml/2014/10/28/1056 > > Maybe Takashi Iwai will get around to it one day. It was not clear to me whether I should apply it individually from others in the whole thread. Your description looked as if it makes sense only with ARM's bitrev8 support. So, again: should I apply this now to my tree? Takashi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754513AbaKNGzP (ORCPT ); Fri, 14 Nov 2014 01:55:15 -0500 Received: from smtprelay0237.hostedemail.com ([216.40.44.237]:55767 "EHLO smtprelay.hostedemail.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754336AbaKNGzN (ORCPT ); Fri, 14 Nov 2014 01:55:13 -0500 X-Session-Marker: 6A6F6540706572636865732E636F6D X-Spam-Summary: 50,0,0,,d41d8cd98f00b204,joe@perches.com,:::::::::::::::::,RULES_HIT:41:355:379:541:599:800:960:967:973:982:988:989:1260:1277:1311:1313:1314:1345:1359:1373:1437:1515:1516:1518:1534:1543:1593:1594:1605:1711:1730:1747:1777:1792:2110:2198:2199:2393:2525:2553:2560:2563:2682:2685:2693:2828:2859:2933:2937:2939:2942:2945:2947:2951:2954:3022:3138:3139:3140:3141:3142:3622:3865:3866:3867:3870:3871:3872:3873:3874:3934:3936:3938:3941:3944:3947:3950:3953:3956:3959:4321:4605:4641:5007:6119:6120:6261:6691:7808:7903:9010:9025:10004:10400:10848:10967:11026:11232:11473:11658:11914:12043:12050:12291:12438:12517:12519:12555:12663:12740:14096:14097:21060:21080,0,RBL:none,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fn,MSBL:0,DNSBL:none,Custom_rules:0:0:0 X-HE-Tag: dolls49_101c5312fe838 X-Filterd-Recvd-Size: 4953 Message-ID: <1415948109.5912.12.camel@perches.com> Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction From: Joe Perches To: Takashi Iwai Cc: Russell King - ARM Linux , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Date: Thu, 13 Nov 2014 22:55:09 -0800 In-Reply-To: References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> Content-Type: text/plain; charset="ISO-8859-1" X-Mailer: Evolution 3.12.7-0ubuntu1 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > At Thu, 13 Nov 2014 16:05:30 -0800, > Joe Perches wrote: > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > This patch add bitrev.h file to support rbit instruction, > > > > so that we can do bitrev operation by hardware. > > > > Signed-off-by: Yalin Wang > > > > --- > > > > arch/arm/Kconfig | 1 + > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > 2 files changed, 22 insertions(+) > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > index 89c4b5c..be92b3b 100644 > > > > --- a/arch/arm/Kconfig > > > > +++ b/arch/arm/Kconfig > > > > @@ -28,6 +28,7 @@ config ARM > > > > select HANDLE_DOMAIN_IRQ > > > > select HARDIRQS_SW_RESEND > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > you've loaded the patch system up with patches for other parts of the > > > kernel tree for which I am not responsible for. As such, I can't take > > > those patches without the sub-tree maintainer acking them. Also, the > > > commit text in those patches look weird: > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > Use the inline function instead of directly indexing the array. > > > > > > This allows some architectures with hardware instructions for bit > > > reversals to eliminate the array. > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > Why is Joe signing off on these patches? > > > Shouldn't his entry be an Acked-by: ? > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > I created 2 patches that converted direct uses of byte_rev_table > > to that bitrev8 static inline. One of them is already in -next > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > The other hasn't been applied. > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > Maybe Takashi Iwai will get around to it one day. > > It was not clear to me whether I should apply it individually from > others in the whole thread. Your description looked as if it makes > sense only with ARM's bitrev8 support. > > So, again: should I apply this now to my tree? I it would be good to apply even if the bitrev patch for arm is never applied. $ git grep -w bitrev8 | wc -l 110 vs this last direct use of byte_rev_table. cheers, Joe From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754613AbaKNHDF (ORCPT ); Fri, 14 Nov 2014 02:03:05 -0500 Received: from cantor2.suse.de ([195.135.220.15]:52879 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754506AbaKNHDD (ORCPT ); Fri, 14 Nov 2014 02:03:03 -0500 Date: Fri, 14 Nov 2014 08:03:01 +0100 Message-ID: From: Takashi Iwai To: Joe Perches Cc: Russell King - ARM Linux , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction In-Reply-To: <1415948109.5912.12.camel@perches.com> References: <35FD53F367049845BC99AC72306C23D103E010D18261@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18264@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <1415948109.5912.12.camel@perches.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI/1.14.6 (Maruoka) FLIM/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL/10.8 Emacs/24.4 (x86_64-suse-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI 1.14.6 - "Maruoka") Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org At Thu, 13 Nov 2014 22:55:09 -0800, Joe Perches wrote: > > On Fri, 2014-11-14 at 07:37 +0100, Takashi Iwai wrote: > > At Thu, 13 Nov 2014 16:05:30 -0800, > > Joe Perches wrote: > > > > > > On Thu, 2014-11-13 at 23:53 +0000, Russell King - ARM Linux wrote: > > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > > > This patch add bitrev.h file to support rbit instruction, > > > > > so that we can do bitrev operation by hardware. > > > > > Signed-off-by: Yalin Wang > > > > > --- > > > > > arch/arm/Kconfig | 1 + > > > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > > > 2 files changed, 22 insertions(+) > > > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > > > index 89c4b5c..be92b3b 100644 > > > > > --- a/arch/arm/Kconfig > > > > > +++ b/arch/arm/Kconfig > > > > > @@ -28,6 +28,7 @@ config ARM > > > > > select HANDLE_DOMAIN_IRQ > > > > > select HARDIRQS_SW_RESEND > > > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > > > > > Looking at this, this is just wrong. Take a moment to consider what > > > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > > > > > > > Second point (which isn't obvious from your submissions on-list) is that > > > > you've loaded the patch system up with patches for other parts of the > > > > kernel tree for which I am not responsible for. As such, I can't take > > > > those patches without the sub-tree maintainer acking them. Also, the > > > > commit text in those patches look weird: > > > > > > > > 6fire: Convert byte_rev_table uses to bitrev8 > > > > > > > > Use the inline function instead of directly indexing the array. > > > > > > > > This allows some architectures with hardware instructions for bit > > > > reversals to eliminate the array. > > > > > > > > Signed-off-by: Joe Perches <(address hidden)> > > > > Signed-off-by: Yalin Wang <(address hidden)> > > > > > > > > Why is Joe signing off on these patches? > > > > Shouldn't his entry be an Acked-by: ? > > > > > > I didn't sign off on or ack the "add bitrev.h" patch. > > > > > > I created 2 patches that converted direct uses of byte_rev_table > > > to that bitrev8 static inline. One of them is already in -next > > > > > > 7a1283d8f5298437a454ec477384dcd9f9f88bac carl9170: Convert byte_rev_table uses to bitrev8 > > > > > > The other hasn't been applied. > > > > > > https://lkml.org/lkml/2014/10/28/1056 > > > > > > Maybe Takashi Iwai will get around to it one day. > > > > It was not clear to me whether I should apply it individually from > > others in the whole thread. Your description looked as if it makes > > sense only with ARM's bitrev8 support. > > > > So, again: should I apply this now to my tree? > > I it would be good to apply even if the > bitrev patch for arm is never applied. > > $ git grep -w bitrev8 | wc -l > 110 > > vs > > this last direct use of byte_rev_table. Alright, I picked up your original patch and merged. thanks, Takashi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754934AbaKNJwZ (ORCPT ); Fri, 14 Nov 2014 04:52:25 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:39383 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754643AbaKNJwW (ORCPT ); Fri, 14 Nov 2014 04:52:22 -0500 Date: Fri, 14 Nov 2014 09:52:06 +0000 From: Russell King - ARM Linux To: Joe Perches Cc: Takashi Iwai , "Wang, Yalin" , "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114095205.GF4042@n2100.arm.linux.org.uk> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <1415923530.4223.17.camel@perches.com> <20141114001720.GD4042@n2100.arm.linux.org.uk> <1415925943.4141.1.camel@perches.com> <20141114011832.GE4042@n2100.arm.linux.org.uk> <1415928394.4141.3.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1415928394.4141.3.camel@perches.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 13, 2014 at 05:26:34PM -0800, Joe Perches wrote: > On Fri, 2014-11-14 at 01:18 +0000, Russell King - ARM Linux wrote: > > On Thu, Nov 13, 2014 at 04:45:43PM -0800, Joe Perches wrote: > > > I think you shouldn't apply these patches or updated > > > ones either until all the current uses are converted. > > > > Where are the dependencies mentioned? > > I mentioned it when these patches (which are not > mine btw), were submitted the second time. Yes, I'm well aware that the author of the ARM patches are Yalin Wang. > https://lkml.org/lkml/2014/10/27/69 > > > How do I get to know when all > > the dependencies are met? > > No idea. > > > Who is tracking the dependencies? > > Not me. Right, what that means is that no one is doing that. What you've also said in this thread now is that the ARM patches should not be applied until all the other users are converted. As those patches are going via other trees, that means the ARM patches can only be applied _after_ the next merge window _if_ all maintainers pick up the previous set. As I'm not tracking the status of what other maintainers do, I'm simply going to avoid applying these patches until after the next merge window and hope that the other maintainers pick the dependent patches up and get them in during the next merge window. If not, I guess we'll see compile breakage. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965150AbaKNJ61 (ORCPT ); Fri, 14 Nov 2014 04:58:27 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:39394 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754727AbaKNJ6Y (ORCPT ); Fri, 14 Nov 2014 04:58:24 -0500 Date: Fri, 14 Nov 2014 09:58:12 +0000 From: Russell King - ARM Linux To: "Wang, Yalin" Cc: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20141114095812.GG4042@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Nov 14, 2014 at 10:01:34AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > Sent: Friday, November 14, 2014 7:53 AM > > To: Wang, Yalin > > > On Fri, Oct 31, 2014 at 01:42:44PM +0800, Wang, Yalin wrote: > > > This patch add bitrev.h file to support rbit instruction, so that we > > > can do bitrev operation by hardware. > > > Signed-off-by: Yalin Wang > > > --- > > > arch/arm/Kconfig | 1 + > > > arch/arm/include/asm/bitrev.h | 21 +++++++++++++++++++++ > > > 2 files changed, 22 insertions(+) > > > create mode 100644 arch/arm/include/asm/bitrev.h > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > > 89c4b5c..be92b3b 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -28,6 +28,7 @@ config ARM > > > select HANDLE_DOMAIN_IRQ > > > select HARDIRQS_SW_RESEND > > > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > > > + select HAVE_ARCH_BITREVERSE if (CPU_V7M || CPU_V7) > > > > Looking at this, this is just wrong. Take a moment to consider what > > happens if we build a kernel which supports both ARMv6 _and_ ARMv7 CPUs. > > What happens if an ARMv6 CPU tries to execute an rbit instruction? > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? Absolutely it is. > I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? Yes. > If there is problem like you said, > How about this solution: > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) That would work. > For this patch, > I just cherry-pick from Joe, > If you are not responsible for this part, > I will submit to the maintainers for these patches . > Sorry for that . I think you need to discuss with Joe how Joe would like his patches handled. However, it seems that Joe already sent his patches to the appropriate maintainers, and they have been applying those patches themselves. Since your generic ARM changes depend on these patches being accepted first, this means is that I can't apply the generic ARM changes until those other patches have hit mainline, otherwise things are going to break. So, when you come to submit the latest set of patches to the patch system, please do so only after these dependent patches have been merged into mainline so that they don't get accidentally applied before hand and break the two drivers that Joe mentioned. Thanks. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753413AbaKQCjI (ORCPT ); Sun, 16 Nov 2014 21:39:08 -0500 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:7593 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752141AbaKQCjG convert rfc822-to-8bit (ORCPT ); Sun, 16 Nov 2014 21:39:06 -0500 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" CC: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Mon, 17 Nov 2014 10:38:58 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: Ac//8Y3gfHXz4vZxRTGitDF3ewZNIwCHdBrw Message-ID: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18265@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18266@CNBJMBX05.corpusers.net> <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> In-Reply-To: <20141114095812.GG4042@n2100.arm.linux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, November 14, 2014 5:58 PM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > > Is it possible to build a kernel that support both CPU_V6 and CPU_V7? > > Absolutely it is. > > > I mean in Kconfig, CPU_V6 = y and CPU_V7 = y ? > > Yes. > > > If there is problem like you said, > > How about this solution: > > select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > That would work. > OK, I will submit a patch for this change. > > For this patch, > > I just cherry-pick from Joe, > > If you are not responsible for this part, I will submit to the > > maintainers for these patches . > > Sorry for that . > > I think you need to discuss with Joe how Joe would like his patches handled. > However, it seems that Joe already sent his patches to the appropriate > maintainers, and they have been applying those patches themselves. > > Since your generic ARM changes depend on these patches being accepted first, > this means is that I can't apply the generic ARM changes until those other > patches have hit mainline, otherwise things are going to break. So, when > you come to submit the latest set of patches to the patch system, please do > so only after these dependent patches have been merged into mainline so > that they don't get accidentally applied before hand and break the two > drivers that Joe mentioned. Joe has submitted patches to maintainers, So we need wait for them to be accepted . Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757143AbbAHSlO (ORCPT ); Thu, 8 Jan 2015 13:41:14 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:52974 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752022AbbAHSlM (ORCPT ); Thu, 8 Jan 2015 13:41:12 -0500 Date: Thu, 8 Jan 2015 18:40:59 +0000 From: Russell King - ARM Linux To: "Wang, Yalin" Cc: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150108184059.GZ12302@n2100.arm.linux.org.uk> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > Joe has submitted patches to maintainers, > So we need wait for them to be accepted . I ran these patches through my autobuilder, and while most builds didn't seem to be a problem, the randconfigs found errors: /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode `rbit r3,r2' /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode `rbit r0,r1' make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode `rbit r2,r2' make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode `rbit r2,r2' /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode `rbit r1,r1' /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode `rbit ip,ip' /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode `rbit r3,r3' /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode `rbit r5,r5' /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode `rbit lr,lr' /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode `rbit r0,r0' /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode `rbit r3,r3' make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 The root cause is that the kernel being built is supposed to support both ARMv7 and ARMv6K CPUs. However, "rbit" is only available on ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753518AbbAICQm (ORCPT ); Thu, 8 Jan 2015 21:16:42 -0500 Received: from cnbjrel01.sonyericsson.com ([219.141.167.165]:5177 "EHLO cnbjrel01.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751890AbbAICQl convert rfc822-to-8bit (ORCPT ); Thu, 8 Jan 2015 21:16:41 -0500 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" CC: "'Will Deacon'" , "'Ard Biesheuvel'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 9 Jan 2015 10:16:32 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: AdArcq8uzjbeRP0XTp2yrVmbjjbdhgAPqq6A Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> References: <20141030120127.GC32589@arm.com> <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> In-Reply-To: <20150108184059.GZ12302@n2100.arm.linux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, January 09, 2015 2:41 AM > To: Wang, Yalin > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Mon, Nov 17, 2014 at 10:38:58AM +0800, Wang, Yalin wrote: > > Joe has submitted patches to maintainers, So we need wait for them to > > be accepted . > > I ran these patches through my autobuilder, and while most builds didn't > seem to be a problem, the randconfigs found errors: > > /tmp/ccbiuDjS.s:137: Error: selected processor does not support ARM mode > `rbit r3,r2' > /tmp/ccbiuDjS.s:145: Error: selected processor does not support ARM mode > `rbit r0,r1' > make[4]: *** [drivers/iio/amplifiers/ad8366.o] Error 1 > > /tmp/ccFhnoO3.s:6789: Error: selected processor does not support ARM mode > `rbit r2,r2' > make[4]: *** [drivers/mtd/devices/docg3.o] Error 1 > > /tmp/cckMf2pp.s:239: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/cckMf2pp.s:241: Error: selected processor does not support ARM mode > `rbit r2,r2' > /tmp/cckMf2pp.s:248: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/cckMf2pp.s:250: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nvidia.o] Error 1 > > /tmp/ccTgULsO.s:1151: Error: selected processor does not support ARM mode > `rbit r1,r1' > /tmp/ccTgULsO.s:1158: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1164: Error: selected processor does not support ARM mode > `rbit ip,ip' > /tmp/ccTgULsO.s:1166: Error: selected processor does not support ARM mode > `rbit r3,r3' > /tmp/ccTgULsO.s:1227: Error: selected processor does not support ARM mode > `rbit r5,r5' > /tmp/ccTgULsO.s:1229: Error: selected processor does not support ARM mode > `rbit lr,lr' > /tmp/ccTgULsO.s:1236: Error: selected processor does not support ARM mode > `rbit r0,r0' > /tmp/ccTgULsO.s:1238: Error: selected processor does not support ARM mode > `rbit r3,r3' > make[5]: *** [drivers/video/fbdev/nvidia/nv_accel.o] Error 1 > > The root cause is that the kernel being built is supposed to support both > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > In the patch that you applied: 8205/1 add bitrev.h file to support rbit instruction I have add : + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? Then will not build hardware rbit instruction, isn't it ? Thanks From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757530AbbAILLF (ORCPT ); Fri, 9 Jan 2015 06:11:05 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:54902 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754100AbbAILLD (ORCPT ); Fri, 9 Jan 2015 06:11:03 -0500 Date: Fri, 9 Jan 2015 11:10:48 +0000 From: Russell King - ARM Linux To: "Wang, Yalin" Cc: "'Ard Biesheuvel'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150109111048.GE12302@n2100.arm.linux.org.uk> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > -----Original Message----- > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > Sent: Friday, January 09, 2015 2:41 AM > > To: Wang, Yalin > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > > kernel@lists.infradead.org' > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > > > The root cause is that the kernel being built is supposed to support both > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > In the patch that you applied: > 8205/1 add bitrev.h file to support rbit instruction > > I have add : > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? > Then will not build hardware rbit instruction, isn't it ? The config has: CONFIG_CPU_PJ4=y # CONFIG_CPU_V6 is not set CONFIG_CPU_V6K=y CONFIG_CPU_V7=y CONFIG_CPU_32v6=y CONFIG_CPU_32v6K=y CONFIG_CPU_32v7=y And no, the CONFIG_CPU_V* flags refer to the CPUs. The CONFIG_CPU_32v* symbols refer to the CPU architectures. -- FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932979AbbAIMlB (ORCPT ); Fri, 9 Jan 2015 07:41:01 -0500 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:3349 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932419AbbAIMlA convert rfc822-to-8bit (ORCPT ); Fri, 9 Jan 2015 07:41:00 -0500 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" CC: "'Ard Biesheuvel'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 9 Jan 2015 20:40:56 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: AdAr/PXsSIMtzQSaQvaNR/yTI7onlQACpIuA Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> References: <20141030135749.GE32589@arm.com> <35FD53F367049845BC99AC72306C23D103E010D18272@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> In-Reply-To: <20150109111048.GE12302@n2100.arm.linux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Friday, January 09, 2015 7:11 PM > To: Wang, Yalin > Cc: 'Ard Biesheuvel'; 'Will Deacon'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Fri, Jan 09, 2015 at 10:16:32AM +0800, Wang, Yalin wrote: > > > -----Original Message----- > > > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > > > Sent: Friday, January 09, 2015 2:41 AM > > > To: Wang, Yalin > > > Cc: 'Will Deacon'; 'Ard Biesheuvel'; 'linux-kernel@vger.kernel.org'; > > > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; > > > 'linux-arm- kernel@lists.infradead.org' > > > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit > > > instruction > > > > > > The root cause is that the kernel being built is supposed to support > > > both > > > ARMv7 and ARMv6K CPUs. However, "rbit" is only available on > > > ARMv6T2 (thumb2) and ARMv7, and not plain ARMv6 or ARMv6K CPUs. > > > > > In the patch that you applied: > > 8205/1 add bitrev.h file to support rbit instruction > > > > I have add : > > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6) > > > > If you build kernel support ARMv6K, should CONFIG_CPU_V6=y, isn't it ? > > Then will not build hardware rbit instruction, isn't it ? > > The config has: > > CONFIG_CPU_PJ4=y > # CONFIG_CPU_V6 is not set > CONFIG_CPU_V6K=y > CONFIG_CPU_V7=y > CONFIG_CPU_32v6=y > CONFIG_CPU_32v6K=y > CONFIG_CPU_32v7=y > > And no, the CONFIG_CPU_V* flags refer to the CPUs. The > CONFIG_CPU_32v* symbols refer to the CPU architectures. > Oh, I see, How about change like this: + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6K) I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&$B!!(B!CPU_ARM940T ? Another solution is: + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) By the way, I am not clear about the difference between CPU_V6 and CPU_V6K, could you tell me? :) Thank you From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753928AbbANQiQ (ORCPT ); Wed, 14 Jan 2015 11:38:16 -0500 Received: from gw-1.arm.linux.org.uk ([78.32.30.217]:40003 "EHLO pandora.arm.linux.org.uk" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751331AbbANQiO (ORCPT ); Wed, 14 Jan 2015 11:38:14 -0500 Date: Wed, 14 Jan 2015 16:38:00 +0000 From: Russell King - ARM Linux To: "Wang, Yalin" Cc: "'Ard Biesheuvel'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Message-ID: <20150114163800.GZ12302@n2100.arm.linux.org.uk> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 09, 2015 at 08:40:56PM +0800, Wang, Yalin wrote: > Oh, I see, > How about change like this: > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && !CPU_V6K) > I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI &&　!CPU_ARM940T ? > > Another solution is: > + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 && !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) > > By the way, I am not clear about the difference between CPU_V6 and CPU_V6K, could you tell me? :) I think select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 is sufficient - we don't support mixing pre-v6 and v6+ CPU architectures into a single kernel. -- FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up according to speedtest.net. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932298AbbAPBrE (ORCPT ); Thu, 15 Jan 2015 20:47:04 -0500 Received: from cnbjrel02.sonyericsson.com ([219.141.167.166]:19203 "EHLO cnbjrel02.sonyericsson.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752184AbbAPBrC (ORCPT ); Thu, 15 Jan 2015 20:47:02 -0500 From: "Wang, Yalin" To: "'Russell King - ARM Linux'" CC: "'Ard Biesheuvel'" , "'Will Deacon'" , "'linux-kernel@vger.kernel.org'" , "'akinobu.mita@gmail.com'" , "'linux-mm@kvack.org'" , "'Joe Perches'" , "'linux-arm-kernel@lists.infradead.org'" Date: Fri, 16 Jan 2015 09:42:23 +0800 Subject: RE: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Topic: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction Thread-Index: AdAwGH+GkFWyCyF6SCq88Q1ePFZX1QBFSNzw Message-ID: <35FD53F367049845BC99AC72306C23D103EDAF89E1B0@CNBJMBX05.corpusers.net> References: <35FD53F367049845BC99AC72306C23D103E010D18273@CNBJMBX05.corpusers.net> <35FD53F367049845BC99AC72306C23D103E010D18275@CNBJMBX05.corpusers.net> <20141113235322.GC4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E010D1829B@CNBJMBX05.corpusers.net> <20141114095812.GG4042@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103E688B313C6@CNBJMBX05.corpusers.net> <20150108184059.GZ12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E195@CNBJMBX05.corpusers.net> <20150109111048.GE12302@n2100.arm.linux.org.uk> <35FD53F367049845BC99AC72306C23D103EDAF89E198@CNBJMBX05.corpusers.net> <20150114163800.GZ12302@n2100.arm.linux.org.uk> In-Reply-To: <20150114163800.GZ12302@n2100.arm.linux.org.uk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id t0G1l9KO019220 > -----Original Message----- > From: Russell King - ARM Linux [mailto:linux@arm.linux.org.uk] > Sent: Thursday, January 15, 2015 12:38 AM > To: Wang, Yalin > Cc: 'Ard Biesheuvel'; 'Will Deacon'; 'linux-kernel@vger.kernel.org'; > 'akinobu.mita@gmail.com'; 'linux-mm@kvack.org'; 'Joe Perches'; 'linux-arm- > kernel@lists.infradead.org' > Subject: Re: [RFC V6 2/3] arm:add bitrev.h file to support rbit instruction > > On Fri, Jan 09, 2015 at 08:40:56PM +0800, Wang, Yalin wrote: > > Oh, I see, > > How about change like this: > > + select HAVE_ARCH_BITREVERSE if ((CPU_V7M || CPU_V7) && !CPU_V6 && > > +!CPU_V6K) > > I am not sure if I also need add some older CPU types like !CPU_ARM9TDMI > &&　!CPU_ARM940T ? > > > > Another solution is: > > + select HAVE_ARCH_BITREVERSE if ((CPU_32V7M || CPU_32V7) && !CPU_32V6 > > +&& !CPU_32V5 && !CPU_32V4 && !CPU_32V4T && !CPU_32V3) > > > > By the way, I am not clear about the difference between CPU_V6 and > > CPU_V6K, could you tell me? :) > > I think > > select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 > > is sufficient - we don't support mixing pre-v6 and v6+ CPU architectures > into a single kernel. > Ok, I will re-send a patch. Thanks {.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I