Re: [PATCH v3 00/19] usb: dwc3: add support for AMD Nolan SoC

[Felipe Balbi <balbi@ti.com>]

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Hi,

On Tue, Oct 28, 2014 at 07:54:21PM +0800, Huang Rui wrote:
> Hi,
> 
> The series of patches add AMD Nolan (NL) SoC support for DesignWare USB3
> OTG IP with PCI bus glue layer. This controller supported hibernation, LPM
> erratum and used the 2.80a IP version and amd own phy. Current
> implementation support both simulation and SoC platform. And already tested
> with gadget zero and msc tool. It works well on file storage gadget.
> 
> 
> These patches are generated on balbi/testing/next
> 
> Changes from v2 -> v3
> - Confirmed these quirks will be needed in product level
> - Move AMD configuration patch to the last one with all quirk flags
> - Make all quirks as 1-bit field instead of single-bits on a 32-bit
>   variable
> - Add all quirks DeviceTree counterparts
> - Make LPM erratum configurable
> - Add PCI ID into pci_ids.h because it will be used both on PCI and DWC3
>   device driver.
> 
> Changes from v1 -> v2
> - Remove dual role function temporarily
> - Add pci quirk to avoid to bind with xhci driver
> - Distinguish between simulation board and soc
> - Break down all the special quirks

In all patches touching DeviceTree, you should add the matching binding
documentation under Documentation/devicetree/bindings/usb/dwc3.txt

There are still a few cases where you're clipping words too harshly, for
example tx_deemph doesn't look very intuitive, if you spell it out as
tx_deemphasis, it's easier to read. Remember that humans will be the
ones fiddling with those quirks.

A few of your patches I have fixed myself and they now sit on
testing/next, please rebase your remaining changes there and make sure
to add DeviceTree documentation.

When resending, please resend the entire series (even the ones I have
already taken) because you also didn't Cc devicetree mailing list.

cheers

-- 
balbi

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