Re: [PATCH] drm/i915: Make sample_c messages go faster on Haswell.

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Kenneth Graunke <kenneth@whitecape.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Make sample_c messages go faster on Haswell.
Date: Thu, 30 Oct 2014 10:50:03 +0200	[thread overview]
Message-ID: <20141030085003.GQ10649@intel.com> (raw)
In-Reply-To: <1414620763-2841-1-git-send-email-kenneth@whitecape.org>

On Wed, Oct 29, 2014 at 03:12:43PM -0700, Kenneth Graunke wrote:
> Haswell significantly improved the performance of sampler_c messages,
> but the optimization appears to be off by default.  Later platforms
> remove this bit, and apparently always enable the optimization.
> 
> Improves performance in "Counter Strike: Global Offensive" by 18%
> at default settings on Iris Pro.  No Piglit regressions.

Nice. We need more bits like this ;)

> 
> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 +
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 77fce96..340821a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5952,6 +5952,7 @@ enum punit_power_well {
>  #define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
>  
>  #define HALF_SLICE_CHICKEN3		0xe184
> +#define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
>  #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>  #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a69eba..50c72a7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5736,6 +5736,10 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_GT_MODE,
>  		   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
>  
> +	/* Make sample_c messages faster. */

I found a name for it in the w/a database.

WaSampleCChickenBitEnable:hsw

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +	I915_WRITE(HALF_SLICE_CHICKEN3,
> +		   _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
> +
>  	/* WaSwitchSolVfFArbitrationPriority:hsw */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  
> -- 
> 2.1.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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