diff for duplicates of <20141030113808.GA32589@arm.com> diff --git a/a/1.txt b/N1/1.txt index 3e03c9f..55c3c87 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -9,7 +9,7 @@ On Wed, Oct 29, 2014 at 09:13:40PM +0000, Mitchel Humpherys wrote: > enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 > and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. > -> Signed-off-by: Mitchel Humpherys <mitchelh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> +> Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> > --- > Changes since v6: > - added missing lock @@ -138,7 +138,7 @@ That probably wants to be ~0xfffULL for LPAE kernels. With that: - Acked-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Acked-by: Will Deacon <will.deacon@arm.com> I'm not sure how we should merge this, given the dependency on patch 1. If you can get some acks there, then we can work out whether to take this via diff --git a/a/content_digest b/N1/content_digest index 144da54..7fa9324 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,12 +1,9 @@ "ref\01414617220-21493-1-git-send-email-mitchelh@codeaurora.org\0" "ref\01414617220-21493-3-git-send-email-mitchelh@codeaurora.org\0" - "ref\01414617220-21493-3-git-send-email-mitchelh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" - "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" - "Subject\0Re: [PATCH v7 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH v7 2/2] iommu/arm-smmu: add support for iova_to_phys through ATS1PR\0" "Date\0Thu, 30 Oct 2014 11:38:08 +0000\0" - "To\0Mitchel Humpherys <mitchelh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Cc\0iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>" - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Wed, Oct 29, 2014 at 09:13:40PM +0000, Mitchel Humpherys wrote:\n" @@ -20,7 +17,7 @@ "> enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1\n" "> and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.\n" "> \n" - "> Signed-off-by: Mitchel Humpherys <mitchelh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\n" + "> Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>\n" "> ---\n" "> Changes since v6:\n" "> - added missing lock\n" @@ -149,7 +146,7 @@ "\n" "With that:\n" "\n" - " Acked-by: Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\n" + " Acked-by: Will Deacon <will.deacon@arm.com>\n" "\n" "I'm not sure how we should merge this, given the dependency on patch 1. If\n" "you can get some acks there, then we can work out whether to take this via\n" @@ -159,4 +156,4 @@ "\n" Will -01bee4a6e3ea732a6fb4c686cfd006e2794c5c196416fe06f49fa30e270dbb69 +0c17ca9fcd8ac63b82959573634bcc50d79fb1ab875d923d7aec02ee368f0a12
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