From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH v2 04/17] drm/tegra: dsi: Add ganged mode support Date: Tue, 4 Nov 2014 16:49:44 +0100 Message-ID: <20141104154942.GB1840@ulmo.nvidia.com> References: <1415006868-318-1-git-send-email-thierry.reding@gmail.com> <1415006868-318-4-git-send-email-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1971293178==" Return-path: Received: from mail-pd0-f173.google.com (mail-pd0-f173.google.com [209.85.192.173]) by gabe.freedesktop.org (Postfix) with ESMTP id 227326E0A0 for ; Tue, 4 Nov 2014 07:49:52 -0800 (PST) Received: by mail-pd0-f173.google.com with SMTP id v10so13872869pde.4 for ; Tue, 04 Nov 2014 07:49:51 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul Cc: dri-devel List-Id: dri-devel@lists.freedesktop.org --===============1971293178== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="TakKZr9L6Hm6aLOc" Content-Disposition: inline --TakKZr9L6Hm6aLOc Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Nov 03, 2014 at 01:30:38PM -0500, Sean Paul wrote: > On Mon, Nov 3, 2014 at 4:27 AM, Thierry Reding = wrote: > > From: Thierry Reding > > > > Implement ganged mode support for the Tegra DSI driver. The DSI host > > controller to gang up with is specified via a phandle in the device tree > > and the resolved DSI host controller used for the programming of the > > ganged-mode registers. > > >=20 > There's a lot in here that is not specifically ganging-support, such > as adding the transfer callback and command mode, as well as pulling > out functionality into helper functions. It might make things a little > clearer to split this up into a few patches. I'll leave that up to > you. I think I tried to do that a while back, but things got really complicated so I abandonned that effort. I'll give it another shot and see what I can come up with. > > diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c [...] > > -static int tegra_output_dsi_enable(struct tegra_output *output) > > +static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned in= t start, > > + unsigned int size) > > +{ > > + u32 value; > > + > > + tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); > > + tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); >=20 > You might want to add "size =3D size & 0xFFFF;" before performing this wr= ite. Actually according to register documentation the mask even needs to be 0x1fff, so that's a good idea. Alternatively I guess we could check the size earlier to make sure that we can actually support it. Thierry --TakKZr9L6Hm6aLOc Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBAgAGBQJUWPWWAAoJEN0jrNd/PrOhepsP/iDgBdDtrV2TMkAfkx8GocYB cPDRkaJ65HabI+5OH+B6F06auUgcF1ls0e+GPZzW263sbSU0y3Y4W42D/nQ+VYbP DVdZq1t5DsTl8IjspUyOd1oV2w+QXV45NP9uRfSyGAau4zVhVdvgaxP0fFHDxpP4 v2lcWpMQgsa24QeBi/PYbBEzXBeNnAxlk/ida3zK/vWdFIt1r+7xtPwI8UwtP9hH hhAjXczmmAneumo4wkwvkbbNuDLs52LDO/j7gf0FpPf4nbbQ6jaG1VsEpo4dPBJx tzku05ohuMTRBpJgnRZMMPSHsL7Dgrh0LSuZfLfJZ0ivUSbapmAkbBPCe+AqFf9m QwoBMSfYChk/9i8clvbvQ47ti/8NL6I0zgB7ezTnwnIHDzJH/7Y/1VbvNKLB/FR9 yn3/gHb1d+JA9uGFBnGNFDuOHmKf+b+mTEW8Bn6+DEKn9Gx/DDMPso7sKOgZFTac Lp1KJpckULUSWEuZQbiudK2CzQ9ldg/6qGYmwKI8F7+y4PdZQAidKSFIpsSNt/va YccPemyg4rPz5SZGFqL40QZRbsFvnhm3u2qztcu6j32NXvsuew//0chcYSF/Rx8c Y6Fovf3iXa2/N+0gnlbzw3L2sm0QfOdAgG9nIkVL5De7cIGF6aE4VZA+0hJjvkiI y3cJUEEoXffx+URBz7Dc =Yqgn -----END PGP SIGNATURE----- --TakKZr9L6Hm6aLOc-- --===============1971293178== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK --===============1971293178==--