[RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Manuel Lauss]

Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
---
Compiles with binutils 2.23 and current git head, tested with alchemy (mips32r1)
and maltasmvp_defconfig (64bit)

Tests with MSA and other extensions also appreciated!

v6: #undef fp so that the preprocessor does not replace the fp in 
	.set fp=64 with $30...  Fixes 64bit build.

v5: fixed issues with code for 32bit mips32r2 using .set mips64r2 outlined
    by Matthew: what the code really wants is 64bit float support, but not
    64bit mips code.

v4: fixed issues outlined by Markos and Matthew.

v3: incorporate Maciej's suggestions:
	- detect if gas can handle -msoft-float and ".set hardfloat"
	- apply .set hardfloat only where really necessary

v2: cover more files

This was introduced in binutils commit  351cdf24d223290b15fa991e5052ec9e9bd1e284
("[MIPS] Implement O32 FPXX, FP64 and FP64A ABI extensions").

 arch/mips/Makefile                  |  9 +++++++++
 arch/mips/include/asm/asmmacro-32.h |  6 ++++++
 arch/mips/include/asm/asmmacro.h    | 18 ++++++++++++++++++
 arch/mips/include/asm/fpregdef.h    | 14 ++++++++++++++
 arch/mips/include/asm/fpu.h         |  4 ++--
 arch/mips/include/asm/mipsregs.h    | 11 ++++++++++-
 arch/mips/kernel/branch.c           |  8 ++------
 arch/mips/kernel/genex.S            |  1 +
 arch/mips/kernel/r2300_fpu.S        |  6 ++++++
 arch/mips/kernel/r2300_switch.S     |  5 +++++
 arch/mips/kernel/r4k_fpu.S          | 27 +++++++++++++++++++++++++--
 arch/mips/kernel/r4k_switch.S       | 15 ++++++++++++++-
 arch/mips/kernel/r6000_fpu.S        |  5 +++++
 13 files changed, 117 insertions(+), 12 deletions(-)

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 23cb948..5807647 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux			+= -G 0 -static -n -nostdlib
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls
 
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
+
 cflags-y += -ffreestanding
 
 #
diff --git a/arch/mips/include/asm/asmmacro-32.h b/arch/mips/include/asm/asmmacro-32.h
index e38c281..cdac7b3 100644
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
 #include <asm/mipsregs.h>
 
 	.macro	fpu_save_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	cfc1	\tmp,  fcr31
 	swc1	$f0,  THREAD_FPR0_LS64(\thread)
 	swc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -47,9 +49,12 @@
 	swc1	$f30, THREAD_FPR30_LS64(\thread)
 	swc1	$f31, THREAD_FPR31_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set pop
 	.endm
 
 	.macro	fpu_restore_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	lwc1	$f0,  THREAD_FPR0_LS64(\thread)
 	lwc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -84,6 +89,7 @@
 	lwc1	$f30, THREAD_FPR30_LS64(\thread)
 	lwc1	$f31, THREAD_FPR31_LS64(\thread)
 	ctc1	\tmp, fcr31
+	.set pop
 	.endm
 
 	.macro	cpu_save_nonscratch thread
diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index cd9a98b..6caf876 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -57,6 +57,8 @@
 #endif /* CONFIG_CPU_MIPSR2 */
 
 	.macro	fpu_save_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp, fcr31
 	sdc1	$f0,  THREAD_FPR0_LS64(\thread)
 	sdc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -75,11 +77,13 @@
 	sdc1	$f28, THREAD_FPR28_LS64(\thread)
 	sdc1	$f30, THREAD_FPR30_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 
 	.macro	fpu_save_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	sdc1	$f1,  THREAD_FPR1_LS64(\thread)
 	sdc1	$f3,  THREAD_FPR3_LS64(\thread)
 	sdc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -110,6 +114,8 @@
 	.endm
 
 	.macro	fpu_restore_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	ldc1	$f0,  THREAD_FPR0_LS64(\thread)
 	ldc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -133,6 +139,7 @@
 	.macro	fpu_restore_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	ldc1	$f1,  THREAD_FPR1_LS64(\thread)
 	ldc1	$f3,  THREAD_FPR3_LS64(\thread)
 	ldc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -277,6 +284,7 @@
 	.macro	cfcmsa	rd, cs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	CFC_MSA_INSN | (\cs << 11)
 	move	\rd, $1
@@ -286,6 +294,7 @@
 	.macro	ctcmsa	cd, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	move	$1, \rs
 	.word	CTC_MSA_INSN | (\cd << 6)
 	.set	pop
@@ -294,6 +303,7 @@
 	.macro	ld_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	add	$1, \base, \off
 	.word	LDD_MSA_INSN | (\wd << 6)
 	.set	pop
@@ -302,6 +312,7 @@
 	.macro	st_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	add	$1, \base, \off
 	.word	STD_MSA_INSN | (\wd << 6)
 	.set	pop
@@ -310,6 +321,7 @@
 	.macro	copy_u_w	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
@@ -320,6 +332,7 @@
 	.macro	copy_u_d	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
@@ -330,6 +343,7 @@
 	.macro	insert_w	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -339,6 +353,7 @@
 	.macro	insert_d	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -381,6 +396,7 @@
 	st_d	31, THREAD_FPR31, \thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	cfcmsa	$1, MSA_CSR
 	sw	$1, THREAD_MSA_CSR(\thread)
 	.set	pop
@@ -389,6 +405,7 @@
 	.macro	msa_restore_all	thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	lw	$1, THREAD_MSA_CSR(\thread)
 	ctcmsa	MSA_CSR, $1
 	.set	pop
@@ -441,6 +458,7 @@
 	.macro	msa_init_all_upper
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	not	$1, zero
 	msa_init_upper	0
 	.set	pop
diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 429481f..f184ba0 100644
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
 
 #include <asm/sgidefs.h>
 
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 4d0aeda..dd56241 100644
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -145,8 +145,8 @@ static inline void lose_fpu(int save)
 	if (is_msa_enabled()) {
 		if (save) {
 			save_msa(current);
-			asm volatile("cfc1 %0, $31"
-				: "=r"(current->thread.fpu.fcr31));
+			current->thread.fpu.fcr31 =
+					read_32bit_cp1_register(CP1_STATUS);
 		}
 		disable_msa();
 		clear_thread_flag(TIF_USEDMSA);
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index cf3b580..b46cd22 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1324,7 +1324,7 @@ do {									\
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)					\
+#define _read_32bit_cp1_register(source, gas_hardfloat)			\
 ({									\
 	int __res;							\
 									\
@@ -1334,12 +1334,21 @@ do {									\
 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
 	"	# like Octeon.					\n"	\
 	"	.set	mips1					\n"	\
+	"	"STR(gas_hardfloat)"				\n"	\
 	"	cfc1	%0,"STR(source)"			\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res));						\
 	__res;								\
 })
 
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#endif
+
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 7b2df22..4d7d99d 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
 		case mm_bc1t_op:
 			preempt_disable();
 			if (is_fpu_owner())
-				asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 			else
 				fcr31 = current->thread.fpu.fcr31;
 			preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
 	case cop1_op:
 		preempt_disable();
 		if (is_fpu_owner())
-			asm volatile(
-				".set push\n"
-				"\t.set mips1\n"
-				"\tcfc1\t%0,$31\n"
-				"\t.set pop" : "=r" (fcr31));
+		        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 		else
 			fcr31 = current->thread.fpu.fcr31;
 		preempt_enable();
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ac35e12..a5e26dd 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	.set	mips1
+	SET_HARDFLOAT
 	cfc1	a1, fcr31
 	li	a2, ~(0x3f << 12)
 	and	a2, a1
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index f31063d..5ce3b74 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
 	.set	mips1
 	/* Save floating point context */
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	cfc1	t1,fcr31
 	EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
 	EX(sw	t1,(SC_FPC_CSR)(a0))
 	cfc1	t0,$0				# implementation/version
 	jr	ra
+	.set	pop
 	.set	nomacro
 	 EX(sw	t0,(SC_FPC_EIR)(a0))
 	.set	macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
  * stack frame which might have been changed by the user.
  */
 LEAF(_restore_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	EX(lw t0,(SC_FPC_CSR)(a0))
 	EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
 	EX(lwc1 $f31,(SC_FPREGS+248)(a0))
 	jr	ra
 	 ctc1	t0,fcr31
+	.set	pop
 	END(_restore_fp_context)
 	.set	reorder
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 20b7b04..435ea65 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
 	mtc1	t0, $f31
 	jr	ra
 	END(_init_fpu)
+
+	.set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 8352523..6c160c6 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 	.macro	EX insn, reg, src
 	.set	push
+	SET_HARDFLOAT
 	.set	nomacro
 .ex\@:	\insn	\reg, \src
 	.set	pop
@@ -33,12 +37,17 @@
 	.set	arch=r4000
 
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
+	.set	pop
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
 1:	.set	pop
 #endif
 
+	.set push
+	SET_HARDFLOAT
 	/* Store the 16 even double precision registers */
 	EX	sdc1 $f0, SC_FPREGS+0(a0)
 	EX	sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
 	EX	sw t1, SC_FPC_CSR(a0)
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
 	/* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 
 	mfc0	t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
 	EX	sw t1, SC32_FPC_CSR(a0)
 	cfc1	t0, $0				# implementation/version
 	EX	sw t0, SC32_FPC_EIR(a0)
+	.set pop
 
 	jr	ra
 	 li	v0, 0					# success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
 	EX	ldc1 $f31, SC_FPREGS+248(a0)
 1:	.set pop
 #endif
+	.set push
+	SET_HARDFLOAT
 	EX	ldc1 $f0, SC_FPREGS+0(a0)
 	EX	ldc1 $f2, SC_FPREGS+16(a0)
 	EX	ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
 	EX	ldc1 $f28, SC_FPREGS+224(a0)
 	EX	ldc1 $f30, SC_FPREGS+240(a0)
 	ctc1	t1, fcr31
+	.set pop
 	jr	ra
 	 li	v0, 0					# success
 	END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 LEAF(_restore_fp_context32)
 	/* Restore an o32 sigcontext.  */
+	.set push
+	SET_HARDFLOAT
 	EX	lw t1, SC32_FPC_CSR(a0)
 
 	mfc0	t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
 	ctc1	t1, fcr31
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_restore_fp_context32)
 #endif
 
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 4c4ec18..64591e6 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
 
 #include <asm/asmmacro.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
@@ -65,8 +68,12 @@
 	bgtz	a3, 1f
 
 	/* Save 128b MSA vector context + scalar FP control & status. */
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 	msa_save_all	a0
+	.set pop	/* SET_HARDFLOAT */
+
 	sw	t1, THREAD_FCR31(a0)
 	b	2f
 
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
 
 #ifdef CONFIG_CPU_MIPS32_R2
 	.set    push
-	.set    mips64r2
+	.set    mips32r2
+	.set	fp=64
 	sll     t0, t0, 5			# is Status.FR set?
 	bgez    t0, 1f				# no: skip setting upper 32b
 
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
 #endif
 	jr	ra
 	END(_init_fpu)
+
+	.set pop	/* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
index da0fbe4..4707738 100644
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
 
 	.set	noreorder
 	.set	mips2
+	.set	push
+	SET_HARDFLOAT
+
 	/* Save floating point context */
 	LEAF(_save_fp_context)
 	mfc0	t0,CP0_STATUS
@@ -85,3 +88,5 @@
 1:	jr	ra
 	 nop
 	END(_restore_fp_context)
+
+	.set pop	/* SET_HARDFLOAT */
-- 
2.1.2

Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Markos Chandras]

On 10/31/2014 04:03 PM, Manuel Lauss wrote:
> Starting with version 2.24.51.20140728 MIPS binutils complain loudly
> about mixing soft-float and hard-float object files, leading to this
> build failure since GCC is invoked with "-msoft-float" on MIPS:
> 
> {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
>   LD      arch/mips/alchemy/common/built-in.o
> mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
>  uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
>  arch/mips/alchemy/common/sleeper.o uses -mhard-float
> 
> To fix this, we detect if GAS is new enough to support "-msoft-float" command
> option, and if it does, we can let GCC pass it to GAS;  but then we also need
> to sprinkle the files which make use of floating point registers with the
> necessary ".set hardfloat" directives.
> 
> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
> ---
> Compiles with binutils 2.23 and current git head, tested with alchemy (mips32r1)
> and maltasmvp_defconfig (64bit)
> 
> Tests with MSA and other extensions also appreciated!
> 
> v6: #undef fp so that the preprocessor does not replace the fp in 
> 	.set fp=64 with $30...  Fixes 64bit build.

Technically speaking, a maltasmvp_defconfig selects CONFIG_32BIT=y so
it's still a 32-bit build.
> [...]

Ok the fp problem went away but I still have the even/odd errors with my
tools

arch/mips/kernel/r4k_switch.S: Assembler messages:
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 1
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 3
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 5
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 7
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 9
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 11
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 13
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 15
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 17
arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
was 19

The following patch did not help either:

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 58076472bdd8..b8bb7e170fee 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -56,7 +56,7 @@ ifdef CONFIG_FUNCTION_GRAPH_TRACER
   endif
 endif
 cflags-y += $(call cc-option, -mno-check-zero-division)
-
+cflags-y += -mno-odd-spreg

This is with a regular maltasmvp_defconfig

I guess my gcc version is newer than yours. Matthew?

-- 
markos

Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Manuel Lauss]

I didn't encounter this error with what will be gcc-4.9.3.


Manuel

On Fri, Oct 31, 2014 at 5:13 PM, Markos Chandras
<Markos.Chandras@imgtec.com> wrote:
> On 10/31/2014 04:03 PM, Manuel Lauss wrote:
>> Starting with version 2.24.51.20140728 MIPS binutils complain loudly
>> about mixing soft-float and hard-float object files, leading to this
>> build failure since GCC is invoked with "-msoft-float" on MIPS:
>>
>> {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
>>   LD      arch/mips/alchemy/common/built-in.o
>> mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
>>  uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
>>  arch/mips/alchemy/common/sleeper.o uses -mhard-float
>>
>> To fix this, we detect if GAS is new enough to support "-msoft-float" command
>> option, and if it does, we can let GCC pass it to GAS;  but then we also need
>> to sprinkle the files which make use of floating point registers with the
>> necessary ".set hardfloat" directives.
>>
>> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
>> ---
>> Compiles with binutils 2.23 and current git head, tested with alchemy (mips32r1)
>> and maltasmvp_defconfig (64bit)
>>
>> Tests with MSA and other extensions also appreciated!
>>
>> v6: #undef fp so that the preprocessor does not replace the fp in
>>       .set fp=64 with $30...  Fixes 64bit build.
>
> Technically speaking, a maltasmvp_defconfig selects CONFIG_32BIT=y so
> it's still a 32-bit build.
>> [...]
>
> Ok the fp problem went away but I still have the even/odd errors with my
> tools
>
> arch/mips/kernel/r4k_switch.S: Assembler messages:
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 1
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 3
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 5
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 7
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 9
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 11
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 13
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 15
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 17
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 19
>
> The following patch did not help either:
>
> diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> index 58076472bdd8..b8bb7e170fee 100644
> --- a/arch/mips/Makefile
> +++ b/arch/mips/Makefile
> @@ -56,7 +56,7 @@ ifdef CONFIG_FUNCTION_GRAPH_TRACER
>    endif
>  endif
>  cflags-y += $(call cc-option, -mno-check-zero-division)
> -
> +cflags-y += -mno-odd-spreg
>
> This is with a regular maltasmvp_defconfig
>
> I guess my gcc version is newer than yours. Matthew?
>
> --
> markos

RE: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Matthew Fortune]

> > Tests with MSA and other extensions also appreciated!
> >
> > v6: #undef fp so that the preprocessor does not replace the fp in
> > 	.set fp=64 with $30...  Fixes 64bit build.
> 
> Technically speaking, a maltasmvp_defconfig selects CONFIG_32BIT=y so
> it's still a 32-bit build.
> > [...]
> 
> Ok the fp problem went away but I still have the even/odd errors with my
> tools
> 
> arch/mips/kernel/r4k_switch.S: Assembler messages:
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 1
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 3
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 5
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 7
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 9
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 11
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 13
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 15
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 17
> arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> was 19

Could you send me the .s and compile flags?

Matthew 

RE: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Matthew Fortune]

Hi all,

The issues Markos has seen will be resolved in the toolchain so this
patch is good to go.

Matthew

> -----Original Message-----
> From: Manuel Lauss [mailto:manuel.lauss@gmail.com]
> Sent: 31 October 2014 16:23
> To: Markos Chandras
> Cc: Linux-MIPS; Matthew Fortune; Maciej W. Rozycki; Ralf Baechle
> Subject: Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+
> 
> I didn't encounter this error with what will be gcc-4.9.3.
> 
> 
> Manuel
> 
> On Fri, Oct 31, 2014 at 5:13 PM, Markos Chandras
> <Markos.Chandras@imgtec.com> wrote:
> > On 10/31/2014 04:03 PM, Manuel Lauss wrote:
> >> Starting with version 2.24.51.20140728 MIPS binutils complain loudly
> >> about mixing soft-float and hard-float object files, leading to this
> >> build failure since GCC is invoked with "-msoft-float" on MIPS:
> >>
> >> {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
> >>   LD      arch/mips/alchemy/common/built-in.o
> >> mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-
> in.o
> >>  uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
> >>  arch/mips/alchemy/common/sleeper.o uses -mhard-float
> >>
> >> To fix this, we detect if GAS is new enough to support "-msoft-float"
> command
> >> option, and if it does, we can let GCC pass it to GAS;  but then we
> also need
> >> to sprinkle the files which make use of floating point registers with
> the
> >> necessary ".set hardfloat" directives.
> >>
> >> Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
> >> ---
> >> Compiles with binutils 2.23 and current git head, tested with alchemy
> (mips32r1)
> >> and maltasmvp_defconfig (64bit)
> >>
> >> Tests with MSA and other extensions also appreciated!
> >>
> >> v6: #undef fp so that the preprocessor does not replace the fp in
> >>       .set fp=64 with $30...  Fixes 64bit build.
> >
> > Technically speaking, a maltasmvp_defconfig selects CONFIG_32BIT=y so
> > it's still a 32-bit build.
> >> [...]
> >
> > Ok the fp problem went away but I still have the even/odd errors with my
> > tools
> >
> > arch/mips/kernel/r4k_switch.S: Assembler messages:
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 1
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 3
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 5
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 7
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 9
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 11
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 13
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 15
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 17
> > arch/mips/kernel/r4k_switch.S:81: Error: float register should be even,
> > was 19
> >
> > The following patch did not help either:
> >
> > diff --git a/arch/mips/Makefile b/arch/mips/Makefile
> > index 58076472bdd8..b8bb7e170fee 100644
> > --- a/arch/mips/Makefile
> > +++ b/arch/mips/Makefile
> > @@ -56,7 +56,7 @@ ifdef CONFIG_FUNCTION_GRAPH_TRACER
> >    endif
> >  endif
> >  cflags-y += $(call cc-option, -mno-check-zero-division)
> > -
> > +cflags-y += -mno-odd-spreg
> >
> > This is with a regular maltasmvp_defconfig
> >
> > I guess my gcc version is newer than yours. Matthew?
> >
> > --
> > markos

Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Ralf Baechle]

On Fri, Oct 31, 2014 at 05:03:14PM +0100, Manuel Lauss wrote:

With this patch applied and binutils 2.24 I'm getting this:

[...]
{standard input}: Assembler messages:
{standard input}:4248: Error: opcode not supported on this processor: mips1
+(mips1) `cfc1 $2,$31'
make[1]: *** [arch/mips/math-emu/cp1emu.o] Error 1
make: *** [arch/mips/math-emu] Error 2
make: *** Waiting for unfinished jobs....

for all defconfigs.

  Ralf

RE: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Matthew Fortune]

> +(mips1) `cfc1 $2,$31'
> make[1]: *** [arch/mips/math-emu/cp1emu.o] Error 1
> make: *** [arch/mips/math-emu] Error 2
> make: *** Waiting for unfinished jobs....

This is the offending code in cp1emu.c:

                        if (is_fpu_owner())
                                asm volatile(
                                        ".set push\n"
                                        "\t.set mips1\n"
                                        "\tcfc1\t%0,$31\n"
                                        "\t.set pop" : "=r" (fcr31));
                        else
                                fcr31 = current->thread.fpu.fcr31;
                        preempt_enable();

I'm not sure how this can have built with binutils 2.23 (as indicated by
Manuel and not built with 2.24). The reason this works with the latest
version of binutils 2.24.x is that cfc1 has been reclassified as not an
FPU instruction.

This just needs the hardfloat annotation adding via the macro as in the
other cases.

Thanks,
Matthew

Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Markos Chandras]

On 11/07/2014 11:05 AM, Matthew Fortune wrote:
>> +(mips1) `cfc1 $2,$31'
>> make[1]: *** [arch/mips/math-emu/cp1emu.o] Error 1
>> make: *** [arch/mips/math-emu] Error 2
>> make: *** Waiting for unfinished jobs....
> 
> This is the offending code in cp1emu.c:
> 
>                         if (is_fpu_owner())
>                                 asm volatile(
>                                         ".set push\n"
>                                         "\t.set mips1\n"
>                                         "\tcfc1\t%0,$31\n"
>                                         "\t.set pop" : "=r" (fcr31));
>                         else
>                                 fcr31 = current->thread.fpu.fcr31;
>                         preempt_enable();
> 
> I'm not sure how this can have built with binutils 2.23 (as indicated by
> Manuel and not built with 2.24). The reason this works with the latest
> version of binutils 2.24.x is that cfc1 has been reclassified as not an
> FPU instruction.
> 
> This just needs the hardfloat annotation adding via the macro as in the
> other cases.
> 
> Thanks,
> Matthew
> 
I am confused about this comment. The problem is reproducible with the
latest Mentor toolchain which uses the following gas
GNU assembler version 2.24.51 (mips-linux-gnu) using BFD version
(Sourcery CodeBench Lite 2014.05-27) 2.24.51.20140217.

I am not sure how Manuel's patch triggered this problem on Mentor to be
honest.

-- 
markos

Re: [RFC PATCH v6] MIPS: fix build with binutils 2.24.51+

[Manuel Lauss]

On Fri, Nov 7, 2014 at 12:05 PM, Matthew Fortune
<Matthew.Fortune@imgtec.com> wrote:
>> +(mips1) `cfc1 $2,$31'
>> make[1]: *** [arch/mips/math-emu/cp1emu.o] Error 1
>> make: *** [arch/mips/math-emu] Error 2
>> make: *** Waiting for unfinished jobs....
>
> This is the offending code in cp1emu.c:
>
>                         if (is_fpu_owner())
>                                 asm volatile(
>                                         ".set push\n"
>                                         "\t.set mips1\n"
>                                         "\tcfc1\t%0,$31\n"
>                                         "\t.set pop" : "=r" (fcr31));
>                         else
>                                 fcr31 = current->thread.fpu.fcr31;
>                         preempt_enable();
>
>
> I'm not sure how this can have built with binutils 2.23 (as indicated by
> Manuel and not built with 2.24). The reason this works with the latest
> version of binutils 2.24.x is that cfc1 has been reclassified as not an
> FPU instruction.
>
> This just needs the hardfloat annotation adding via the macro as in the
> other cases.


Oh I know how to fix it.  However I'm unsure why I didn't run into this
while testing.  I've repeatedly built a cavium-octeon, malta and my
alchemy defconfigs
and never hit this.

I'll send out a revised patch shortly.

Thank you!
        Manuel