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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA
Date: Fri, 7 Nov 2014 16:04:43 +0100	[thread overview]
Message-ID: <201411071604.44091.marex@denx.de> (raw)
In-Reply-To: <1415360272-13249-2-git-send-email-sr@denx.de>

On Friday, November 07, 2014 at 12:37:49 PM, Stefan Roese wrote:

Hi!

> This driver is cloned from the Altera Rockerboard.org U-Boot
> repository. I used this git tag: ACDS14.0.1_REL_GSRD_RC2. With Some
> modification to support the U-Boot driver model (DM).
> 
> As mentioned above, in this new version I ported this driver to the
> new driver model (DM). One big advantage of this move is that now
> multiple SPI drivers can be enabled on one platform. And since the
> SoCFPGA also has the Designware SPI master controller integrated,
> this feature is really needed to support both controllers.
> 
> Because of this, this series needs the DT support for SoCFPGA
> to be applied. For DT based probing in the SPI DM.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Chin Liang See <clsee@altera.com>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Vince Bridgers <vbridger@altera.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

[...]

> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> new file mode 100644
> index 0000000..c9a6142
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi.h
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (C) 2012
> + * Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef __CADENCE_QSPI_H__
> +#define __CADENCE_QSPI_H__
> +
> +#define CQSPI_IS_ADDR(cmd_len)		(cmd_len > 1 ? 1 : 0)
> +
> +#define CQSPI_NO_DECODER_MAX_CS		4
> +#define CQSPI_DECODER_MAX_CS		16
> +#define CQSPI_READ_CAPTURE_MAX_DELAY	16
> +
> +struct cadence_spi_platdata {
> +	unsigned int	max_hz;
> +	void		*regbase;
> +	void		*ahbbase;
> +
> +	u32		page_size;
> +	u32		block_size;
> +	u32		tshsl_ns;
> +	u32		tsd2d_ns;
> +	u32		tchsh_ns;
> +	u32		tslch_ns;
> +};
> +
> +struct cadence_spi_priv {
> +	void		*regbase;
> +	void		*ahbbase;
> +	size_t		cmd_len;
> +	u8		cmd_buf[32];
> +	size_t		data_len;
> +
> +	int		qspi_is_init;
> +	unsigned int	qspi_calibrated_hz;
> +	unsigned int	qspi_calibrated_cs;
> +};
> +
> +/* Functions call declaration */
> +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
> +void cadence_qspi_apb_controller_enable(void *reg_base_addr);
> +void cadence_qspi_apb_controller_disable(void *reg_base_addr);

Is it really necessary to export all these functions ?

[...]

> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c new file mode 100644
> index 0000000..00a115f
> --- /dev/null
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -0,0 +1,898 @@
> +/*
> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are
> met: + *  - Redistributions of source code must retain the above copyright
> + *    notice, this list of conditions and the following disclaimer. + * 
> - Redistributions in binary form must reproduce the above copyright + *   
> notice, this list of conditions and the following disclaimer in the + *   
> documentation and/or other materials provided with the distribution. + * 
> - Neither the name of the Altera Corporation nor the
> + *    names of its contributors may be used to endorse or promote products
> + *    derived from this software without specific prior written
> permission. + *
> + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
> IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
> TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
> PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA
> CORPORATION BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
> EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO,
> PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR
> PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF
> LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING
> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS
> SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */

This license is kinda iffy. What is this all about please ?

> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/errno.h>
> +#include "cadence_qspi.h"
> +
> +#define CQSPI_REG_POLL_US			(1) /* 1us */
> +#define CQSPI_REG_RETRY				(10000)
> +#define CQSPI_POLL_IDLE_RETRY			(3)
> +
> +#define CQSPI_FIFO_WIDTH			(4)

These braces around numbers should be fixed, but that's not the current pressing 
issue here.
[...]

  reply	other threads:[~2014-11-07 15:04 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-07 11:37 [U-Boot] [PATCH 0/4 v4] arm: socfpga: Add Cadence QSPI support Stefan Roese
2014-11-07 11:37 ` [U-Boot] [PATCH 1/4 v4] spi: Add Cadence QSPI DM driver used by SoCFPGA Stefan Roese
2014-11-07 15:04   ` Marek Vasut [this message]
2014-11-07 15:26     ` Stefan Roese
2014-11-07 19:56       ` Dinh Nguyen
2014-11-08 12:18         ` Stefan Roese
2014-12-06 12:56           ` Marek Vasut
2014-12-08  8:14             ` Stefan Roese
2016-01-14  2:17               ` Marek Vasut
2014-11-07 17:59   ` Simon Glass
2014-11-07 11:37 ` [U-Boot] [PATCH 2/4 v4] arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi Stefan Roese
2014-11-07 17:21   ` Simon Glass
2014-11-07 17:26     ` Stefan Roese
2014-11-10 10:47       ` Pavel Machek
2014-11-10 15:48         ` Dinh Nguyen
2014-11-07 11:37 ` [U-Boot] [PATCH 3/4 v4] arm: socfpga: dts: Add spi0 alias for Cadence QSPI driver Stefan Roese
2014-11-07 15:06   ` Marek Vasut
2014-11-07 18:02   ` Simon Glass
2014-11-07 11:37 ` [U-Boot] [PATCH 4/4 v4] arm: socfpga: Add Cadence QSPI support to config header Stefan Roese

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