Re: [RFC/PATCH 0/5 v2] mtd:ubi: Read disturb and Data retention handling

[Juergen Borleis <jbe@pengutronix.de>]

Hi Ricard,

On Monday 10 November 2014 14:13:27 Ricard Wanderlof wrote:
> [...]
> These are interesting figures. I must admit I've never seen anything quite
> so bad before.

That leads me to the question if I have done the test in a correct way.

> We use 128 MiB and 256 MiB SLC NAND chips in our products, and as part of
> the device qualification we run a test on a couple of samples where we
> repeatedly read the first four blocks of the flash in an endless loop, and
> measure the number of correctable and uncorrectable errors that occur.
>
> Normally, we can read millions of times before even getting a single bit
> flip. I've currently had a Macronix 128 MiB flash under test, which
> according to the data sheet requires 4-bit ECC, but after 68 million reads
> of the type just mentioned is still performing well with only single-bit
> errors in various places in the test area. (The fact that errors do start
> to occur after a while puts any suspicions of unexpected read caching to
> rest). Admittedly, this is all at room temperature, etc, and only a single
> sample, but it still is quite far from 200 000 reads. Other chips of the
> same sizes that we use which specify 1-bit ECC have a similar performance.
>
> The fact that 512 MiB is worse than 256 MiB is not too surprising, there
> could well be a technology jump between those sizes, with smaller bit
> cells for the larger flash.

I have no idea how the two boards were programmend I run these two tests on. 
Maybe the NAND programming was done in a wrong way which leads to this bad 
result.
On these boards the first 4 MiB area is the 'bootloader area', which must have 
a special layout to enable the ROM code to load the bootloader from it.

I have a bunch of boards here with 128/256/512 MiB NANDs where I can repeat the 
tests. Any recommendations how to setup the NAND before to do the tests again?

jbe

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