From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Nov 2014 00:03:11 +0100 (CET) Received: from down.free-electrons.com ([37.187.137.238]:47375 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S27013146AbaKJXDI406Bt (ORCPT ); Tue, 11 Nov 2014 00:03:08 +0100 Received: by mail.free-electrons.com (Postfix, from userid 106) id 3AF9E745; Tue, 11 Nov 2014 00:03:10 +0100 (CET) Received: from localhost (128-79-216-6.hfc.dyn.abo.bbox.fr [128.79.216.6]) by mail.free-electrons.com (Postfix) with ESMTPSA id E891E743; Tue, 11 Nov 2014 00:03:09 +0100 (CET) Date: Tue, 11 Nov 2014 00:03:01 +0100 From: Alexandre Belloni To: Kevin Cernekee Cc: Kevin Hilman , Thomas Gleixner , Jason Cooper , linux-sh@vger.kernel.org, Florian Fainelli , Ralf Baechle , Sergei Shtylyov , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Maxime Bizon , Jonas Gorski , Linux MIPS Mailing List , nicolas.ferre@atmel.com, Olof Johansson , Arnd Bergmann , Boris Brezillon Subject: Re: [PATCH V4 04/14] genirq: Generic chip: Add big endian I/O accessors Message-ID: <20141110230301.GV4068@piout.net> References: <1415342669-30640-1-git-send-email-cernekee@gmail.com> <1415342669-30640-5-git-send-email-cernekee@gmail.com> <7hy4riogwt.fsf@deeprootsystems.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 43973 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alexandre.belloni@free-electrons.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Adding Boris in Cc: as he wrote that part. On 10/11/2014 at 14:11:44 -0800, Kevin Cernekee wrote : > On Mon, Nov 10, 2014 at 2:00 PM, Kevin Hilman wrote: > > Kevin Cernekee writes: > > > >> Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating > >> the irqchip. > >> > >> Signed-off-by: Kevin Cernekee > > > > I bisected a couple ARM boot failures in next-20141110 on atmel sama5 platforms down to > > this patch, though I'm not quite yet sure how it's causing the failure. > > I'm not getting any console output, so haven't been able to dig deeper > > yet. Maybe the atmel maintainers (Cc'd) can help dig. > > > > I've confirmed that reverting $SUBJECT patch (commit > > b79055952badbd73710685643bab44104f2509ea2) on top of next-20141110 gets > > things booting again. > > > > Also, it only happens with sama5_defconfig, not with multi_v7_defconfig. > > In drivers/irqchip/irq-atmel-aic-common.c I see: > > ret = irq_alloc_domain_generic_chips(domain, 32, 1, name, > handle_level_irq, 0, 0, > IRQCHIP_SKIP_SET_WAKE); > > and IRQCHIP_SKIP_SET_WAKE is (1 << 4), same as IRQ_GC_BE_IO. > > Is it possible that the caller is passing values intended for > irq_chip->flags into a function expecting > irq_domain_chip_generic->gc_flags ? -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Belloni Date: Mon, 10 Nov 2014 23:03:01 +0000 Subject: Re: [PATCH V4 04/14] genirq: Generic chip: Add big endian I/O accessors Message-Id: <20141110230301.GV4068@piout.net> List-Id: References: <1415342669-30640-1-git-send-email-cernekee@gmail.com> <1415342669-30640-5-git-send-email-cernekee@gmail.com> <7hy4riogwt.fsf@deeprootsystems.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Kevin Cernekee Cc: Kevin Hilman , Thomas Gleixner , Jason Cooper , linux-sh@vger.kernel.org, Florian Fainelli , Ralf Baechle , Sergei Shtylyov , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Maxime Bizon , Jonas Gorski , Linux MIPS Mailing List , nicolas.ferre@atmel.com, Olof Johansson , Arnd Bergmann , Boris Brezillon Adding Boris in Cc: as he wrote that part. On 10/11/2014 at 14:11:44 -0800, Kevin Cernekee wrote : > On Mon, Nov 10, 2014 at 2:00 PM, Kevin Hilman wrote: > > Kevin Cernekee writes: > > > >> Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating > >> the irqchip. > >> > >> Signed-off-by: Kevin Cernekee > > > > I bisected a couple ARM boot failures in next-20141110 on atmel sama5 platforms down to > > this patch, though I'm not quite yet sure how it's causing the failure. > > I'm not getting any console output, so haven't been able to dig deeper > > yet. Maybe the atmel maintainers (Cc'd) can help dig. > > > > I've confirmed that reverting $SUBJECT patch (commit > > b79055952badbd73710685643bab44104f2509ea2) on top of next-20141110 gets > > things booting again. > > > > Also, it only happens with sama5_defconfig, not with multi_v7_defconfig. > > In drivers/irqchip/irq-atmel-aic-common.c I see: > > ret = irq_alloc_domain_generic_chips(domain, 32, 1, name, > handle_level_irq, 0, 0, > IRQCHIP_SKIP_SET_WAKE); > > and IRQCHIP_SKIP_SET_WAKE is (1 << 4), same as IRQ_GC_BE_IO. > > Is it possible that the caller is passing values intended for > irq_chip->flags into a function expecting > irq_domain_chip_generic->gc_flags ? -- Alexandre Belloni, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com