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Date:   Tue, 11 Nov 2014 11:05:19 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     Huacai Chen <chenhc@lemote.com>
Cc:     John Crispin <john@phrozen.org>,
        "Steven J. Hill" <Steven.Hill@imgtec.com>,
        linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
        Zhangjin Wu <wuzhangjin@gmail.com>,
        Hongliang Tao <taohl@lemote.com>
Subject: Re: [PATCH V2 04/12] MIPS: Loongson: Introduce and use
 cpu_has_coherent_cache feature
Message-ID: <20141111100518.GC27259@linux-mips.org>
References: <1415081610-25639-1-git-send-email-chenhc@lemote.com>
 <1415081610-25639-5-git-send-email-chenhc@lemote.com>
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On Tue, Nov 04, 2014 at 02:13:25PM +0800, Huacai Chen wrote:

> Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
> feature named cpu_has_coherent_cache and use it to modify MIPS's cache
> flushing functions.

You've modified all the local_* functions which means the r4k_on_each_cpu()
in r4k___flush_cache_all(), r4k_flush_cache_sigtramp() otc. will still be
executed.

Your change is correct - but I think it can be optimized if we can assume
that all CPUs have a coherent cache by moving the check into the caller.

smp_call_function() can be fairly expensive in particular on big systems!

  Ralf