From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org,
Mika Kuoppala <mika.kuoppala@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence
Date: Wed, 12 Nov 2014 13:26:28 +0200 [thread overview]
Message-ID: <20141112112628.GN10649@intel.com> (raw)
In-Reply-To: <20141112092810.GO25711@phenom.ffwll.local>
On Wed, Nov 12, 2014 at 10:28:10AM +0100, Daniel Vetter wrote:
> On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > > From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > >
> > > As per latest pm guide, we need to do this also on
> > > past hsw.
> >
> > Yep, matches the doc.
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Queued for -next, thanks for the patch.
> >
> > BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> > see such a thing documented in the HSW PM guide I have here. Maybe we can
> > just drop the HSW special case?
>
> Iirc (commit message is silent unfortunately) this is for the GT3. And
> since they're 0 on other hsw we've opted for a tricky silent gt3 enabling
> by claiming this is for all of hsw. At least that's the story I remember.
>
> No idea whether bdw gt3 would need this, too. Might be good to
> double-check.
The docs claim these are the same old thread wish result bits ever since
snb.
I just tried intel_reg_read on hsw gt2 and gt3 and both give identical
results to ivb. So my hunch is that we can just drop the hsw special
case.
--
Ville Syrjälä
Intel OTC
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prev parent reply other threads:[~2014-11-12 11:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-10 12:52 [PATCH 0/8] drm-intel-collector - update Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 1/8] drm/i915: Make the physical object coherent with GTT Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 2/8] drm/i915: Specify bsd rings through exec flag Rodrigo Vivi
2014-11-14 0:54 ` Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 3/8] drm/i915: add I915_PARAM_HAS_BSD2 to i915_getparam Rodrigo Vivi
2014-11-14 0:56 ` Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 4/8] drm/i915: Move the ban period onto the context Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 5/8] drm/i915: Add ioctl to set per-context parameters Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 6/8] drm/i915: Put logical pipe_control emission into a helper Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 7/8] drm/i915: Add WaCsStallBeforeStateCacheInvalidate:bdw, chv to logical ring Rodrigo Vivi
2014-11-10 12:52 ` [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence Rodrigo Vivi
2014-11-11 14:57 ` [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw shuang.he
2014-11-11 17:12 ` [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence Ville Syrjälä
2014-11-11 17:26 ` Ville Syrjälä
2014-11-12 9:28 ` Daniel Vetter
2014-11-12 11:26 ` Ville Syrjälä [this message]
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