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Date:   Thu, 13 Nov 2014 11:31:08 +0100
From:   Ralf Baechle <ralf@linux-mips.org>
To:     "Steven J. Hill" <Steven.Hill@imgtec.com>,
        Markos Chandras <markos.chandras@imgtec.com>
Cc:     linux-mips@linux-mips.org
Subject: Re: [PATCH 05/11] MIPS: mm: c-r4k: Ensure CCA is set to non-coherent
 on UP kernels.
Message-ID: <20141113103108.GB13753@linux-mips.org>
References: <1415858743-24492-1-git-send-email-Steven.Hill@imgtec.com>
 <1415858743-24492-6-git-send-email-Steven.Hill@imgtec.com>
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On Thu, Nov 13, 2014 at 12:05:37AM -0600, Steven J. Hill wrote:

> diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
> index 1559360..076e660 100644
> --- a/arch/mips/mm/c-r4k.c
> +++ b/arch/mips/mm/c-r4k.c
> @@ -1595,8 +1595,17 @@ early_param("cca", cca_setup);
>  
>  static void coherency_setup(void)
>  {
> -	if (cca < 0 || cca > 7)
> -		cca = read_c0_config() & CONF_CM_CMASK;
> +	if (cca < 0 || cca > 7) {
> +		/*
> +		 * Set CCA to non-coherent to ensure that the UP kernel
> +		 * behaves properly even on MC processors where the ROM
> +		 * may have prepared the C0 registers for SMP operation.
> +		 */
> +		if (!config_enabled(CONFIG_SMP))
> +			cca = _CACHE_CACHABLE_NONCOHERENT >> _CACHE_SHIFT;
> +		else
> +			cca = read_c0_config() & CONF_CM_CMASK;
> +	}

NAK.  This would trigger falsely on pretty much every SMP platform in
MIPS history except Octeon - with usually fatal consequences.

Is there a performance disadvantage or why is this desirable?

  Ralf